// SPDX-License-Identifier: GPL-2.0-only // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. #include <linux/cleanup.h>#include <linux/module.h>#include <linux/init.h>#include <linux/io.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/clk.h>#include <sound/soc.h>#include <sound/pcm.h>#include <sound/pcm_params.h>#include <sound/soc-dapm.h>#include <sound/tlv.h>#include <linux/of_clk.h>#include <linux/clk-provider.h>#include "lpass-macro-common.h" #define CDC_RX_TOP_TOP_CFG0 (0x0000)#define CDC_RX_TOP_SWR_CTRL (0x0008)#define CDC_RX_TOP_DEBUG (0x000C)#define CDC_RX_TOP_DEBUG_BUS (0x0010)#define CDC_RX_TOP_DEBUG_EN0 (0x0014)#define CDC_RX_TOP_DEBUG_EN1 (0x0018)#define CDC_RX_TOP_DEBUG_EN2 (0x001C)#define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)#define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)#define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)#define CDC_RX_TOP_HPH_LUT_BYPASS_MASK BIT(7)#define CDC_RX_TOP_HPHL_COMP_RD_LSB (0x002C)#define CDC_RX_TOP_HPHL_COMP_RD_MSB (0x0030)#define CDC_RX_TOP_HPHR_COMP_WR_LSB (0x0034)#define CDC_RX_TOP_HPHR_COMP_WR_MSB (0x0038)#define CDC_RX_TOP_HPHR_COMP_LUT (0x003C)#define CDC_RX_TOP_HPHR_COMP_RD_LSB (0x0040)#define CDC_RX_TOP_HPHR_COMP_RD_MSB (0x0044)#define CDC_RX_TOP_DSD0_DEBUG_CFG0 (0x0070)#define CDC_RX_TOP_DSD0_DEBUG_CFG1 (0x0074)#define CDC_RX_TOP_DSD0_DEBUG_CFG2 (0x0078)#define CDC_RX_TOP_DSD0_DEBUG_CFG3 (0x007C)#define CDC_RX_TOP_DSD1_DEBUG_CFG0 (0x0080)#define CDC_RX_TOP_DSD1_DEBUG_CFG1 (0x0084)#define CDC_RX_TOP_DSD1_DEBUG_CFG2 (0x0088)#define CDC_RX_TOP_DSD1_DEBUG_CFG3 (0x008C)#define CDC_RX_TOP_RX_I2S_CTL (0x0090)#define CDC_RX_TOP_TX_I2S2_CTL (0x0094)#define CDC_RX_TOP_I2S_CLK (0x0098)#define CDC_RX_TOP_I2S_RESET (0x009C)#define CDC_RX_TOP_I2S_MUX (0x00A0)#define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (0x0100)#define CDC_RX_CLK_MCLK_EN_MASK BIT(0)#define CDC_RX_CLK_MCLK_ENABLE BIT(0)#define CDC_RX_CLK_MCLK2_EN_MASK BIT(1)#define CDC_RX_CLK_MCLK2_ENABLE BIT(1)#define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0104)#define CDC_RX_FS_MCLK_CNT_EN_MASK BIT(0)#define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0)#define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1)#define CDC_RX_FS_MCLK_CNT_CLR BIT(1)#define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108)#define CDC_RX_SWR_CLK_EN_MASK BIT(0)#define CDC_RX_SWR_RESET_MASK BIT(1)#define CDC_RX_SWR_RESET BIT(1)#define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C)#define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x0110)#define CDC_RX_SOFTCLIP_CRC (0x0140)#define CDC_RX_SOFTCLIP_CLK_EN_MASK BIT(0)#define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (0x0144)#define CDC_RX_SOFTCLIP_EN_MASK BIT(0)#define CDC_RX_INP_MUX_RX_INT0_CFG0 (0x0180)#define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)#define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4)#define CDC_RX_INP_MUX_RX_INT0_CFG1 (0x0184)#define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0)#define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4)#define CDC_RX_INP_MUX_RX_INT1_CFG0 (0x0188)#define CDC_RX_INP_MUX_RX_INT1_CFG1 (0x018C)#define CDC_RX_INP_MUX_RX_INT2_CFG0 (0x0190)#define CDC_RX_INP_MUX_RX_INT2_CFG1 (0x0194)#define CDC_RX_INP_MUX_RX_MIX_CFG4 (0x0198)#define CDC_RX_INP_MUX_RX_MIX_CFG5 (0x019C)#define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x01A0)#define CDC_RX_CLSH_CRC (0x0200)#define CDC_RX_CLSH_CLK_EN_MASK BIT(0)#define CDC_RX_CLSH_DLY_CTRL (0x0204)#define CDC_RX_CLSH_DECAY_CTRL (0x0208)#define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0)#define CDC_RX_CLSH_HPH_V_PA (0x020C)#define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0)#define CDC_RX_CLSH_EAR_V_PA (0x0210)#define CDC_RX_CLSH_HPH_V_HD (0x0214)#define CDC_RX_CLSH_EAR_V_HD (0x0218)#define CDC_RX_CLSH_K1_MSB (0x021C)#define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0)#define CDC_RX_CLSH_K1_LSB (0x0220)#define CDC_RX_CLSH_K2_MSB (0x0224)#define CDC_RX_CLSH_K2_LSB (0x0228)#define CDC_RX_CLSH_IDLE_CTRL (0x022C)#define CDC_RX_CLSH_IDLE_HPH (0x0230)#define CDC_RX_CLSH_IDLE_EAR (0x0234)#define CDC_RX_CLSH_TEST0 (0x0238)#define CDC_RX_CLSH_TEST1 (0x023C)#define CDC_RX_CLSH_OVR_VREF (0x0240)#define CDC_RX_CLSH_CLSG_CTL (0x0244)#define CDC_RX_CLSH_CLSG_CFG1 (0x0248)#define CDC_RX_CLSH_CLSG_CFG2 (0x024C)#define CDC_RX_BCL_VBAT_PATH_CTL (0x0280)#define CDC_RX_BCL_VBAT_CFG (0x0284)#define CDC_RX_BCL_VBAT_ADC_CAL1 (0x0288)#define CDC_RX_BCL_VBAT_ADC_CAL2 (0x028C)#define CDC_RX_BCL_VBAT_ADC_CAL3 (0x0290)#define CDC_RX_BCL_VBAT_PK_EST1 (0x0294)#define CDC_RX_BCL_VBAT_PK_EST2 (0x0298)#define CDC_RX_BCL_VBAT_PK_EST3 (0x029C)#define CDC_RX_BCL_VBAT_RF_PROC1 (0x02A0)#define CDC_RX_BCL_VBAT_RF_PROC2 (0x02A4)#define CDC_RX_BCL_VBAT_TAC1 (0x02A8)#define CDC_RX_BCL_VBAT_TAC2 (0x02AC)#define CDC_RX_BCL_VBAT_TAC3 (0x02B0)#define CDC_RX_BCL_VBAT_TAC4 (0x02B4)#define CDC_RX_BCL_VBAT_GAIN_UPD1 (0x02B8)#define CDC_RX_BCL_VBAT_GAIN_UPD2 (0x02BC)#define CDC_RX_BCL_VBAT_GAIN_UPD3 (0x02C0)#define CDC_RX_BCL_VBAT_GAIN_UPD4 (0x02C4)#define CDC_RX_BCL_VBAT_GAIN_UPD5 (0x02C8)#define CDC_RX_BCL_VBAT_DEBUG1 (0x02CC)#define CDC_RX_BCL_VBAT_GAIN_UPD_MON (0x02D0)#define CDC_RX_BCL_VBAT_GAIN_MON_VAL (0x02D4)#define CDC_RX_BCL_VBAT_BAN (0x02D8)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (0x02DC)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (0x02E0)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (0x02E4)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (0x02E8)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (0x02EC)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (0x02F0)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (0x02F4)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (0x02F8)#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (0x02FC)#define CDC_RX_BCL_VBAT_ATTN1 (0x0300)#define CDC_RX_BCL_VBAT_ATTN2 (0x0304)#define CDC_RX_BCL_VBAT_ATTN3 (0x0308)#define CDC_RX_BCL_VBAT_DECODE_CTL1 (0x030C)#define CDC_RX_BCL_VBAT_DECODE_CTL2 (0x0310)#define CDC_RX_BCL_VBAT_DECODE_CFG1 (0x0314)#define CDC_RX_BCL_VBAT_DECODE_CFG2 (0x0318)#define CDC_RX_BCL_VBAT_DECODE_CFG3 (0x031C)#define CDC_RX_BCL_VBAT_DECODE_CFG4 (0x0320)#define CDC_RX_BCL_VBAT_DECODE_ST (0x0324)#define CDC_RX_INTR_CTRL_CFG (0x0340)#define CDC_RX_INTR_CTRL_CLR_COMMIT (0x0344)#define CDC_RX_INTR_CTRL_PIN1_MASK0 (0x0360)#define CDC_RX_INTR_CTRL_PIN1_STATUS0 (0x0368)#define CDC_RX_INTR_CTRL_PIN1_CLEAR0 (0x0370)#define CDC_RX_INTR_CTRL_PIN2_MASK0 (0x0380)#define CDC_RX_INTR_CTRL_PIN2_STATUS0 (0x0388)#define CDC_RX_INTR_CTRL_PIN2_CLEAR0 (0x0390)#define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0)#define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8)#define CDC_RX_INTR_CTRL_SET0 (0x03D0)#define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n)#define CDC_RX_RX0_RX_PATH_CTL (0x0400)#define CDC_RX_PATH_RESET_EN_MASK BIT(6)#define CDC_RX_PATH_CLK_EN_MASK BIT(5)#define CDC_RX_PATH_CLK_ENABLE BIT(5)#define CDC_RX_PATH_PGA_MUTE_MASK BIT(4)#define CDC_RX_PATH_PGA_MUTE_ENABLE BIT(4)#define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0)#define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n)#define CDC_RX_RXn_COMP_EN_MASK BIT(1)#define CDC_RX_RX0_RX_PATH_CFG0 (0x0404)#define CDC_RX_RXn_CLSH_EN_MASK BIT(6)#define CDC_RX_DLY_ZN_EN_MASK BIT(3)#define CDC_RX_DLY_ZN_ENABLE BIT(3)#define CDC_RX_RXn_HD2_EN_MASK BIT(2)#define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n)#define CDC_RX_RXn_SIDETONE_EN_MASK BIT(4)#define CDC_RX_RX0_RX_PATH_CFG1 (0x0408)#define CDC_RX_RX0_HPH_L_EAR_SEL_MASK BIT(1)#define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n)#define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0)#define CDC_RX_RX0_RX_PATH_CFG2 (0x040C)#define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n)#define CDC_RX_RX0_RX_PATH_CFG3 (0x0410)#define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0)#define CDC_RX_DC_COEFF_SEL_TWO 0x2#define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n)#define CDC_RX_RX0_RX_VOL_CTL (0x0414)#define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n)#define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0)#define CDC_RX_RXn_MIX_RESET_MASK BIT(6)#define CDC_RX_RXn_MIX_RESET BIT(6)#define CDC_RX_RXn_MIX_CLK_EN_MASK BIT(5)#define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418)#define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C)#define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n)#define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420)#define CDC_RX_RX0_RX_PATH_SEC1 (0x0424)#define CDC_RX_RX0_RX_PATH_SEC2 (0x0428)#define CDC_RX_RX0_RX_PATH_SEC3 (0x042C)#define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n)#define CDC_RX_RX0_RX_PATH_SEC4 (0x0430)#define CDC_RX_RX0_RX_PATH_SEC7 (0x0434)#define CDC_RX_RXn_RX_PATH_SEC7(rx, n) \#define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0)#define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2#define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438)#define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C)#define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n) \#define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0)#define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440)#define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444)#define CDC_RX_RX0_RX_PATH_DSM_DATA2 (0x0448)#define CDC_RX_RX0_RX_PATH_DSM_DATA3 (0x044C)#define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450)#define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454)#define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458)/* RX offsets prior to 2.5 codec version */ #define CDC_RX_RX1_RX_PATH_CTL (0x0480)#define CDC_RX_RX1_RX_PATH_CFG0 (0x0484)#define CDC_RX_RX1_RX_PATH_CFG1 (0x0488)#define CDC_RX_RX1_RX_PATH_CFG2 (0x048C)#define CDC_RX_RX1_RX_PATH_CFG3 (0x0490)#define CDC_RX_RX1_RX_VOL_CTL (0x0494)#define CDC_RX_RX1_RX_PATH_MIX_CTL (0x0498)#define CDC_RX_RX1_RX_PATH_MIX_CFG (0x049C)#define CDC_RX_RX1_RX_VOL_MIX_CTL (0x04A0)#define CDC_RX_RX1_RX_PATH_SEC1 (0x04A4)#define CDC_RX_RX1_RX_PATH_SEC2 (0x04A8)#define CDC_RX_RX1_RX_PATH_SEC3 (0x04AC)#define CDC_RX_RXn_HD2_ALPHA_MASK GENMASK(5, 2)#define CDC_RX_RX1_RX_PATH_SEC4 (0x04B0)#define CDC_RX_RX1_RX_PATH_SEC7 (0x04B4)#define CDC_RX_RX1_RX_PATH_MIX_SEC0 (0x04B8)#define CDC_RX_RX1_RX_PATH_MIX_SEC1 (0x04BC)#define CDC_RX_RX1_RX_PATH_DSM_CTL (0x04C0)#define CDC_RX_RX1_RX_PATH_DSM_DATA1 (0x04C4)#define CDC_RX_RX1_RX_PATH_DSM_DATA2 (0x04C8)#define CDC_RX_RX1_RX_PATH_DSM_DATA3 (0x04CC)#define CDC_RX_RX1_RX_PATH_DSM_DATA4 (0x04D0)#define CDC_RX_RX1_RX_PATH_DSM_DATA5 (0x04D4)#define CDC_RX_RX1_RX_PATH_DSM_DATA6 (0x04D8)#define CDC_RX_RX2_RX_PATH_CTL (0x0500)#define CDC_RX_RX2_RX_PATH_CFG0 (0x0504)#define CDC_RX_RX2_CLSH_EN_MASK BIT(4)#define CDC_RX_RX2_DLY_Z_EN_MASK BIT(3)#define CDC_RX_RX2_RX_PATH_CFG1 (0x0508)#define CDC_RX_RX2_RX_PATH_CFG2 (0x050C)#define CDC_RX_RX2_RX_PATH_CFG3 (0x0510)#define CDC_RX_RX2_RX_VOL_CTL (0x0514)#define CDC_RX_RX2_RX_PATH_MIX_CTL (0x0518)#define CDC_RX_RX2_RX_PATH_MIX_CFG (0x051C)#define CDC_RX_RX2_RX_VOL_MIX_CTL (0x0520)#define CDC_RX_RX2_RX_PATH_SEC0 (0x0524)#define CDC_RX_RX2_RX_PATH_SEC1 (0x0528)#define CDC_RX_RX2_RX_PATH_SEC2 (0x052C)#define CDC_RX_RX2_RX_PATH_SEC3 (0x0530)#define CDC_RX_RX2_RX_PATH_SEC4 (0x0534)#define CDC_RX_RX2_RX_PATH_SEC5 (0x0538)#define CDC_RX_RX2_RX_PATH_SEC6 (0x053C)#define CDC_RX_RX2_RX_PATH_SEC7 (0x0540)#define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544)#define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548)#define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C)/* LPASS CODEC version 2.5 rx reg offsets */ #define CDC_2_5_RX_RX1_RX_PATH_CTL (0x04c0)#define CDC_2_5_RX_RX1_RX_PATH_CFG0 (0x04c4)#define CDC_2_5_RX_RX1_RX_PATH_CFG1 (0x04c8)#define CDC_2_5_RX_RX1_RX_PATH_CFG2 (0x04cC)#define CDC_2_5_RX_RX1_RX_PATH_CFG3 (0x04d0)#define CDC_2_5_RX_RX1_RX_VOL_CTL (0x04d4)#define CDC_2_5_RX_RX1_RX_PATH_MIX_CTL (0x04d8)#define CDC_2_5_RX_RX1_RX_PATH_MIX_CFG (0x04dC)#define CDC_2_5_RX_RX1_RX_VOL_MIX_CTL (0x04e0)#define CDC_2_5_RX_RX1_RX_PATH_SEC1 (0x04e4)#define CDC_2_5_RX_RX1_RX_PATH_SEC2 (0x04e8)#define CDC_2_5_RX_RX1_RX_PATH_SEC3 (0x04eC)#define CDC_2_5_RX_RX1_RX_PATH_SEC4 (0x04f0)#define CDC_2_5_RX_RX1_RX_PATH_SEC7 (0x04f4)#define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0 (0x04f8)#define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1 (0x04fC)#define CDC_2_5_RX_RX1_RX_PATH_DSM_CTL (0x0500)#define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1 (0x0504)#define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2 (0x0508)#define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3 (0x050C)#define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4 (0x0510)#define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5 (0x0514)#define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6 (0x0518)#define CDC_2_5_RX_RX2_RX_PATH_CTL (0x0580)#define CDC_2_5_RX_RX2_RX_PATH_CFG0 (0x0584)#define CDC_2_5_RX_RX2_RX_PATH_CFG1 (0x0588)#define CDC_2_5_RX_RX2_RX_PATH_CFG2 (0x058C)#define CDC_2_5_RX_RX2_RX_PATH_CFG3 (0x0590)#define CDC_2_5_RX_RX2_RX_VOL_CTL (0x0594)#define CDC_2_5_RX_RX2_RX_PATH_MIX_CTL (0x0598)#define CDC_2_5_RX_RX2_RX_PATH_MIX_CFG (0x059C)#define CDC_2_5_RX_RX2_RX_VOL_MIX_CTL (0x05a0)#define CDC_2_5_RX_RX2_RX_PATH_SEC0 (0x05a4)#define CDC_2_5_RX_RX2_RX_PATH_SEC1 (0x05a8)#define CDC_2_5_RX_RX2_RX_PATH_SEC2 (0x05aC)#define CDC_2_5_RX_RX2_RX_PATH_SEC3 (0x05b0)#define CDC_2_5_RX_RX2_RX_PATH_SEC4 (0x05b4)#define CDC_2_5_RX_RX2_RX_PATH_SEC5 (0x05b8)#define CDC_2_5_RX_RX2_RX_PATH_SEC6 (0x05bC)#define CDC_2_5_RX_RX2_RX_PATH_SEC7 (0x05c0)#define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0 (0x05c4)#define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1 (0x05c8)#define CDC_2_5_RX_RX2_RX_PATH_DSM_CTL (0x05cC)#define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780)#define CDC_RX_IDLE_DETECT_CFG0 (0x0784)#define CDC_RX_IDLE_DETECT_CFG1 (0x0788)#define CDC_RX_IDLE_DETECT_CFG2 (0x078C)#define CDC_RX_IDLE_DETECT_CFG3 (0x0790)#define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n)#define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0)#define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1)#define CDC_RX_COMPANDERn_HALT_MASK BIT(2)#define CDC_RX_COMPANDER0_CTL0 (0x0800)#define CDC_RX_COMPANDER0_CTL1 (0x0804)#define CDC_RX_COMPANDER0_CTL2 (0x0808)#define CDC_RX_COMPANDER0_CTL3 (0x080C)#define CDC_RX_COMPANDER0_CTL4 (0x0810)#define CDC_RX_COMPANDER0_CTL5 (0x0814)#define CDC_RX_COMPANDER0_CTL6 (0x0818)#define CDC_RX_COMPANDER0_CTL7 (0x081C)#define CDC_RX_COMPANDER1_CTL0 (0x0840)#define CDC_RX_COMPANDER1_CTL1 (0x0844)#define CDC_RX_COMPANDER1_CTL2 (0x0848)#define CDC_RX_COMPANDER1_CTL3 (0x084C)#define CDC_RX_COMPANDER1_CTL4 (0x0850)#define CDC_RX_COMPANDER1_CTL5 (0x0854)#define CDC_RX_COMPANDER1_CTL6 (0x0858)#define CDC_RX_COMPANDER1_CTL7 (0x085C)#define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5)#define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL (0x0A00)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x0A04)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x0A08)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x0A0C)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x0A10)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x0A14)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x0A18)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x0A1C)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x0A20)#define CDC_RX_SIDETONE_IIR0_IIR_CTL (0x0A24)#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28)#define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x0A2C)#define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x0A30)#define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL (0x0A80)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL (0x0A84)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL (0x0A88)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL (0x0A8C)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL (0x0A90)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL (0x0A94)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL (0x0A98)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL (0x0A9C)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL (0x0AA0)#define CDC_RX_SIDETONE_IIR1_IIR_CTL (0x0AA4)#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8)#define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL (0x0AAC)#define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL (0x0AB0)#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (0x0B00)#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (0x0B04)#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (0x0B08)#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (0x0B0C)#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (0x0B10)#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (0x0B14)#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (0x0B18)#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (0x0B1C)#define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x0B40)#define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x0B44)#define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL (0x0B50)#define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 (0x0B54)#define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x0C00)#define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x0C04)#define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x0C40)#define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x0C44)#define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL (0x0C80)#define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (0x0C84)#define CDC_RX_EC_ASRC0_CLK_RST_CTL (0x0D00)#define CDC_RX_EC_ASRC0_CTL0 (0x0D04)#define CDC_RX_EC_ASRC0_CTL1 (0x0D08)#define CDC_RX_EC_ASRC0_FIFO_CTL (0x0D0C)#define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x0D10)#define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x0D14)#define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x0D18)#define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x0D1C)#define CDC_RX_EC_ASRC0_STATUS_FIFO (0x0D20)#define CDC_RX_EC_ASRC1_CLK_RST_CTL (0x0D40)#define CDC_RX_EC_ASRC1_CTL0 (0x0D44)#define CDC_RX_EC_ASRC1_CTL1 (0x0D48)#define CDC_RX_EC_ASRC1_FIFO_CTL (0x0D4C)#define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x0D50)#define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x0D54)#define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x0D58)#define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x0D5C)#define CDC_RX_EC_ASRC1_STATUS_FIFO (0x0D60)#define CDC_RX_EC_ASRC2_CLK_RST_CTL (0x0D80)#define CDC_RX_EC_ASRC2_CTL0 (0x0D84)#define CDC_RX_EC_ASRC2_CTL1 (0x0D88)#define CDC_RX_EC_ASRC2_FIFO_CTL (0x0D8C)#define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB (0x0D90)#define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB (0x0D94)#define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB (0x0D98)#define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB (0x0D9C)#define CDC_RX_EC_ASRC2_STATUS_FIFO (0x0DA0)#define CDC_RX_DSD0_PATH_CTL (0x0F00)#define CDC_RX_DSD0_CFG0 (0x0F04)#define CDC_RX_DSD0_CFG1 (0x0F08)#define CDC_RX_DSD0_CFG2 (0x0F0C)#define CDC_RX_DSD1_PATH_CTL (0x0F80)#define CDC_RX_DSD1_CFG0 (0x0F84)#define CDC_RX_DSD1_CFG1 (0x0F88)#define CDC_RX_DSD1_CFG2 (0x0F8C)#define RX_MAX_OFFSET (0x0F8C)#define MCLK_FREQ 19200000#define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\/* Fractional Rates */ #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\#define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\#define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\#define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\#define RX_MACRO_MAX_DMA_CH_PER_PORT 2#define RX_MACRO_EC_MIX_TX0_MASK 0xf0#define RX_MACRO_EC_MIX_TX1_MASK 0x0f#define RX_MACRO_EC_MIX_TX2_MASK 0x0f#define COMP_MAX_COEFF 25#define RX_NUM_CLKS_MAX 5struct comp_coeff_val {enum {static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = {enum {enum {enum {/* HPH_L */ /* HPH_R */ enum {enum {enum {enum {/* Codec supports 2 IIR filters */ enum {/* Each IIR has 5 Filter Stages */ enum {#define RX_MACRO_IIR_FILTER_SIZE (sizeof (u32) * BAND_MAX)#define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \unsigned long )&(struct wcd_iir_filter_ctl) { \struct interp_sample_rate {int sample_rate;int rate_val;static struct interp_sample_rate sr_val_tbl[] = {/* Matches also rx_macro_mux_text */ enum {enum {struct rx_macro {struct device *dev;int comp_enabled[RX_MACRO_COMP_MAX];/* Main path clock users count */ int main_clk_users[INTERP_MAX];int rx_port_value[RX_MACRO_PORTS_MAX];int rx_mclk_users;int clsh_users;int rx_mclk_cnt;enum lpass_codec_version codec_version;int rxn_reg_stride;int rxn_reg_stride2;bool is_ear_mode_on;bool hph_pwr_mode;bool hph_hd2_mode;struct snd_soc_component *component;unsigned long active_ch_mask[RX_MACRO_MAX_DAIS];unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS];int is_softclip_on;int is_aux_hpf_on;int softclip_clk_users;struct lpass_macro *pds;struct regmap *regmap;struct clk *mclk;struct clk *npl;struct clk *macro;struct clk *dcodec;struct clk *fsgen;struct clk_hw hw;#define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)struct wcd_iir_filter_ctl {unsigned int iir_idx;unsigned int band_idx;struct soc_bytes_ext bytes_ext;static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);static const char * const rx_int_mix_mux_text[] = {"ZERO" , "RX0" , "RX1" , "RX2" , "RX3" , "RX4" , "RX5" static const char * const rx_prim_mix_text[] = {"ZERO" , "DEC0" , "DEC1" , "IIR0" , "IIR1" , "RX0" , "RX1" , "RX2" ,"RX3" , "RX4" , "RX5" static const char * const rx_sidetone_mix_text[] = {"ZERO" , "SRC0" , "SRC1" , "SRC_SUM" static const char * const iir_inp_mux_text[] = {"ZERO" , "DEC0" , "DEC1" , "DEC2" , "DEC3" ,"RX0" , "RX1" , "RX2" , "RX3" , "RX4" , "RX5" static const char * const rx_int_dem_inp_mux_text[] = {"NORMAL_DSM_OUT" , "CLSH_DSM_OUT" ,static const char * const rx_int0_1_interp_mux_text[] = {"ZERO" , "RX INT0_1 MIX1" ,static const char * const rx_int1_1_interp_mux_text[] = {"ZERO" , "RX INT1_1 MIX1" ,static const char * const rx_int2_1_interp_mux_text[] = {"ZERO" , "RX INT2_1 MIX1" ,static const char * const rx_int0_2_interp_mux_text[] = {"ZERO" , "RX INT0_2 MUX" ,static const char * const rx_int1_2_interp_mux_text[] = {"ZERO" , "RX INT1_2 MUX" ,static const char * const rx_int2_2_interp_mux_text[] = {"ZERO" , "RX INT2_2 MUX" ,/* Order must match RX_MACRO_MAX_DAIS enum (offset by 1) */ static const char *const rx_macro_mux_text[] = {"ZERO" , "AIF1_PB" , "AIF2_PB" , "AIF3_PB" , "AIF4_PB" static const char *const rx_macro_hph_pwr_mode_text[] = {"ULP" , "LOHIFI" static const char * const rx_echo_mux_text[] = {"ZERO" , "RX_MIX0" , "RX_MIX1" , "RX_MIX2" static const struct soc_enum rx_macro_hph_pwr_mode_enum =static const struct soc_enum rx_mix_tx2_mux_enum =static const struct soc_enum rx_mix_tx1_mux_enum =static const struct soc_enum rx_mix_tx0_mux_enum =static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4,static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4,static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4,static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4,static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4,static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4,static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2,static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4,static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6,static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,static SOC_ENUM_SINGLE_DECL(rx_2_5_int1_dem_inp_enum, CDC_2_5_RX_RX1_RX_PATH_CFG1, 0,static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);static const struct snd_kcontrol_new rx_mix_tx1_mux ="RX MIX TX1_MUX Mux" , rx_mix_tx1_mux_enum);static const struct snd_kcontrol_new rx_mix_tx2_mux = "RX MIX TX2_MUX Mux" , rx_mix_tx2_mux_enum);static const struct snd_kcontrol_new rx_int0_2_mux ="rx_int0_2" , rx_int0_2_enum);static const struct snd_kcontrol_new rx_int1_2_mux ="rx_int1_2" , rx_int1_2_enum);static const struct snd_kcontrol_new rx_int2_2_mux ="rx_int2_2" , rx_int2_2_enum);static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux ="rx_int0_1_mix_inp0" , rx_int0_1_mix_inp0_enum);static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux ="rx_int0_1_mix_inp1" , rx_int0_1_mix_inp1_enum);static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux ="rx_int0_1_mix_inp2" , rx_int0_1_mix_inp2_enum);static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux ="rx_int1_1_mix_inp0" , rx_int1_1_mix_inp0_enum);static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux ="rx_int1_1_mix_inp1" , rx_int1_1_mix_inp1_enum);static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux ="rx_int1_1_mix_inp2" , rx_int1_1_mix_inp2_enum);static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux ="rx_int2_1_mix_inp0" , rx_int2_1_mix_inp0_enum);static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux ="rx_int2_1_mix_inp1" , rx_int2_1_mix_inp1_enum);static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux ="rx_int2_1_mix_inp2" , rx_int2_1_mix_inp2_enum);static const struct snd_kcontrol_new rx_int0_mix2_inp_mux ="rx_int0_mix2_inp" , rx_int0_mix2_inp_enum);static const struct snd_kcontrol_new rx_int1_mix2_inp_mux ="rx_int1_mix2_inp" , rx_int1_mix2_inp_enum);static const struct snd_kcontrol_new rx_int2_mix2_inp_mux ="rx_int2_mix2_inp" , rx_int2_mix2_inp_enum);static const struct snd_kcontrol_new iir0_inp0_mux ="iir0_inp0" , iir0_inp0_enum);static const struct snd_kcontrol_new iir0_inp1_mux ="iir0_inp1" , iir0_inp1_enum);static const struct snd_kcontrol_new iir0_inp2_mux ="iir0_inp2" , iir0_inp2_enum);static const struct snd_kcontrol_new iir0_inp3_mux ="iir0_inp3" , iir0_inp3_enum);static const struct snd_kcontrol_new iir1_inp0_mux ="iir1_inp0" , iir1_inp0_enum);static const struct snd_kcontrol_new iir1_inp1_mux ="iir1_inp1" , iir1_inp1_enum);static const struct snd_kcontrol_new iir1_inp2_mux ="iir1_inp2" , iir1_inp2_enum);static const struct snd_kcontrol_new iir1_inp3_mux ="iir1_inp3" , iir1_inp3_enum);static const struct snd_kcontrol_new rx_int0_1_interp_mux ="rx_int0_1_interp" , rx_int0_1_interp_enum);static const struct snd_kcontrol_new rx_int1_1_interp_mux ="rx_int1_1_interp" , rx_int1_1_interp_enum);static const struct snd_kcontrol_new rx_int2_1_interp_mux ="rx_int2_1_interp" , rx_int2_1_interp_enum);static const struct snd_kcontrol_new rx_int0_2_interp_mux ="rx_int0_2_interp" , rx_int0_2_interp_enum);static const struct snd_kcontrol_new rx_int1_2_interp_mux ="rx_int1_2_interp" , rx_int1_2_interp_enum);static const struct snd_kcontrol_new rx_int2_2_interp_mux ="rx_int2_2_interp" , rx_int2_2_interp_enum);static const struct snd_kcontrol_new rx_mix_tx0_mux ="RX MIX TX0_MUX Mux" , rx_mix_tx0_mux_enum);static const struct reg_default rx_defaults[] = {/* RX Macro */ static const struct reg_default rx_2_5_defaults[] = {static const struct reg_default rx_pre_2_5_defaults[] = {static bool rx_is_wronly_register(struct device *dev,unsigned int reg)switch (reg) {case CDC_RX_BCL_VBAT_GAIN_UPD_MON:case CDC_RX_INTR_CTRL_CLR_COMMIT:case CDC_RX_INTR_CTRL_PIN1_CLEAR0:case CDC_RX_INTR_CTRL_PIN2_CLEAR0:return true ;return false ;static bool rx_is_volatile_register(struct device *dev, unsigned int reg)/* Update volatile list for rx/tx macros */ switch (reg) {case CDC_RX_TOP_HPHL_COMP_RD_LSB:case CDC_RX_TOP_HPHL_COMP_WR_LSB:case CDC_RX_TOP_HPHL_COMP_RD_MSB:case CDC_RX_TOP_HPHL_COMP_WR_MSB:case CDC_RX_TOP_HPHR_COMP_RD_LSB:case CDC_RX_TOP_HPHR_COMP_WR_LSB:case CDC_RX_TOP_HPHR_COMP_RD_MSB:case CDC_RX_TOP_HPHR_COMP_WR_MSB:case CDC_RX_TOP_DSD0_DEBUG_CFG2:case CDC_RX_TOP_DSD1_DEBUG_CFG2:case CDC_RX_BCL_VBAT_GAIN_MON_VAL:case CDC_RX_BCL_VBAT_DECODE_ST:case CDC_RX_INTR_CTRL_PIN1_STATUS0:case CDC_RX_INTR_CTRL_PIN2_STATUS0:case CDC_RX_COMPANDER0_CTL6:case CDC_RX_COMPANDER1_CTL6:case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:case CDC_RX_EC_ASRC0_STATUS_FIFO:case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:case CDC_RX_EC_ASRC1_STATUS_FIFO:case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:case CDC_RX_EC_ASRC2_STATUS_FIFO:return true ;return false ;static bool rx_pre_2_5_is_rw_register(struct device *dev, unsigned int reg)switch (reg) {case CDC_RX_RX1_RX_PATH_CTL:case CDC_RX_RX1_RX_PATH_CFG0:case CDC_RX_RX1_RX_PATH_CFG1:case CDC_RX_RX1_RX_PATH_CFG2:case CDC_RX_RX1_RX_PATH_CFG3:case CDC_RX_RX1_RX_VOL_CTL:case CDC_RX_RX1_RX_PATH_MIX_CTL:case CDC_RX_RX1_RX_PATH_MIX_CFG:case CDC_RX_RX1_RX_VOL_MIX_CTL:case CDC_RX_RX1_RX_PATH_SEC1:case CDC_RX_RX1_RX_PATH_SEC2:case CDC_RX_RX1_RX_PATH_SEC3:case CDC_RX_RX1_RX_PATH_SEC4:case CDC_RX_RX1_RX_PATH_SEC7:case CDC_RX_RX1_RX_PATH_MIX_SEC0:case CDC_RX_RX1_RX_PATH_MIX_SEC1:case CDC_RX_RX1_RX_PATH_DSM_CTL:case CDC_RX_RX1_RX_PATH_DSM_DATA1:case CDC_RX_RX1_RX_PATH_DSM_DATA2:case CDC_RX_RX1_RX_PATH_DSM_DATA3:case CDC_RX_RX1_RX_PATH_DSM_DATA4:case CDC_RX_RX1_RX_PATH_DSM_DATA5:case CDC_RX_RX1_RX_PATH_DSM_DATA6:case CDC_RX_RX2_RX_PATH_CTL:case CDC_RX_RX2_RX_PATH_CFG0:case CDC_RX_RX2_RX_PATH_CFG1:case CDC_RX_RX2_RX_PATH_CFG2:case CDC_RX_RX2_RX_PATH_CFG3:case CDC_RX_RX2_RX_VOL_CTL:case CDC_RX_RX2_RX_PATH_MIX_CTL:case CDC_RX_RX2_RX_PATH_MIX_CFG:case CDC_RX_RX2_RX_VOL_MIX_CTL:case CDC_RX_RX2_RX_PATH_SEC0:case CDC_RX_RX2_RX_PATH_SEC1:case CDC_RX_RX2_RX_PATH_SEC2:case CDC_RX_RX2_RX_PATH_SEC3:case CDC_RX_RX2_RX_PATH_SEC4:case CDC_RX_RX2_RX_PATH_SEC5:case CDC_RX_RX2_RX_PATH_SEC6:case CDC_RX_RX2_RX_PATH_SEC7:case CDC_RX_RX2_RX_PATH_MIX_SEC0:case CDC_RX_RX2_RX_PATH_MIX_SEC1:case CDC_RX_RX2_RX_PATH_DSM_CTL:return true ;return false ;static bool rx_2_5_is_rw_register(struct device *dev, unsigned int reg)switch (reg) {case CDC_2_5_RX_RX1_RX_PATH_CTL:case CDC_2_5_RX_RX1_RX_PATH_CFG0:case CDC_2_5_RX_RX1_RX_PATH_CFG1:case CDC_2_5_RX_RX1_RX_PATH_CFG2:case CDC_2_5_RX_RX1_RX_PATH_CFG3:case CDC_2_5_RX_RX1_RX_VOL_CTL:case CDC_2_5_RX_RX1_RX_PATH_MIX_CTL:case CDC_2_5_RX_RX1_RX_PATH_MIX_CFG:case CDC_2_5_RX_RX1_RX_VOL_MIX_CTL:case CDC_2_5_RX_RX1_RX_PATH_SEC1:case CDC_2_5_RX_RX1_RX_PATH_SEC2:case CDC_2_5_RX_RX1_RX_PATH_SEC3:case CDC_2_5_RX_RX1_RX_PATH_SEC4:case CDC_2_5_RX_RX1_RX_PATH_SEC7:case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0:case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1:case CDC_2_5_RX_RX1_RX_PATH_DSM_CTL:case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1:case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2:case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3:case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4:case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5:case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6:case CDC_2_5_RX_RX2_RX_PATH_CTL:case CDC_2_5_RX_RX2_RX_PATH_CFG0:case CDC_2_5_RX_RX2_RX_PATH_CFG1:case CDC_2_5_RX_RX2_RX_PATH_CFG2:case CDC_2_5_RX_RX2_RX_PATH_CFG3:case CDC_2_5_RX_RX2_RX_VOL_CTL:case CDC_2_5_RX_RX2_RX_PATH_MIX_CTL:case CDC_2_5_RX_RX2_RX_PATH_MIX_CFG:case CDC_2_5_RX_RX2_RX_VOL_MIX_CTL:case CDC_2_5_RX_RX2_RX_PATH_SEC0:case CDC_2_5_RX_RX2_RX_PATH_SEC1:case CDC_2_5_RX_RX2_RX_PATH_SEC2:case CDC_2_5_RX_RX2_RX_PATH_SEC3:case CDC_2_5_RX_RX2_RX_PATH_SEC4:case CDC_2_5_RX_RX2_RX_PATH_SEC5:case CDC_2_5_RX_RX2_RX_PATH_SEC6:case CDC_2_5_RX_RX2_RX_PATH_SEC7:case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0:case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1:case CDC_2_5_RX_RX2_RX_PATH_DSM_CTL:return true ;return false ;static bool rx_is_rw_register(struct device *dev, unsigned int reg)struct rx_macro *rx = dev_get_drvdata(dev);switch (reg) {case CDC_RX_TOP_TOP_CFG0:case CDC_RX_TOP_SWR_CTRL:case CDC_RX_TOP_DEBUG:case CDC_RX_TOP_DEBUG_BUS:case CDC_RX_TOP_DEBUG_EN0:case CDC_RX_TOP_DEBUG_EN1:case CDC_RX_TOP_DEBUG_EN2:case CDC_RX_TOP_HPHL_COMP_WR_LSB:case CDC_RX_TOP_HPHL_COMP_WR_MSB:case CDC_RX_TOP_HPHL_COMP_LUT:case CDC_RX_TOP_HPHR_COMP_WR_LSB:case CDC_RX_TOP_HPHR_COMP_WR_MSB:case CDC_RX_TOP_HPHR_COMP_LUT:case CDC_RX_TOP_DSD0_DEBUG_CFG0:case CDC_RX_TOP_DSD0_DEBUG_CFG1:case CDC_RX_TOP_DSD0_DEBUG_CFG3:case CDC_RX_TOP_DSD1_DEBUG_CFG0:case CDC_RX_TOP_DSD1_DEBUG_CFG1:case CDC_RX_TOP_DSD1_DEBUG_CFG3:case CDC_RX_TOP_RX_I2S_CTL:case CDC_RX_TOP_TX_I2S2_CTL:case CDC_RX_TOP_I2S_CLK:case CDC_RX_TOP_I2S_RESET:case CDC_RX_TOP_I2S_MUX:case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL:case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL:case CDC_RX_CLK_RST_CTRL_SWR_CONTROL:case CDC_RX_CLK_RST_CTRL_DSD_CONTROL:case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL:case CDC_RX_SOFTCLIP_CRC:case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL:case CDC_RX_INP_MUX_RX_INT0_CFG0:case CDC_RX_INP_MUX_RX_INT0_CFG1:case CDC_RX_INP_MUX_RX_INT1_CFG0:case CDC_RX_INP_MUX_RX_INT1_CFG1:case CDC_RX_INP_MUX_RX_INT2_CFG0:case CDC_RX_INP_MUX_RX_INT2_CFG1:case CDC_RX_INP_MUX_RX_MIX_CFG4:case CDC_RX_INP_MUX_RX_MIX_CFG5:case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0:case CDC_RX_CLSH_CRC:case CDC_RX_CLSH_DLY_CTRL:case CDC_RX_CLSH_DECAY_CTRL:case CDC_RX_CLSH_HPH_V_PA:case CDC_RX_CLSH_EAR_V_PA:case CDC_RX_CLSH_HPH_V_HD:case CDC_RX_CLSH_EAR_V_HD:case CDC_RX_CLSH_K1_MSB:case CDC_RX_CLSH_K1_LSB:case CDC_RX_CLSH_K2_MSB:case CDC_RX_CLSH_K2_LSB:case CDC_RX_CLSH_IDLE_CTRL:case CDC_RX_CLSH_IDLE_HPH:case CDC_RX_CLSH_IDLE_EAR:case CDC_RX_CLSH_TEST0:case CDC_RX_CLSH_TEST1:case CDC_RX_CLSH_OVR_VREF:case CDC_RX_CLSH_CLSG_CTL:case CDC_RX_CLSH_CLSG_CFG1:case CDC_RX_CLSH_CLSG_CFG2:case CDC_RX_BCL_VBAT_PATH_CTL:case CDC_RX_BCL_VBAT_CFG:case CDC_RX_BCL_VBAT_ADC_CAL1:case CDC_RX_BCL_VBAT_ADC_CAL2:case CDC_RX_BCL_VBAT_ADC_CAL3:case CDC_RX_BCL_VBAT_PK_EST1:case CDC_RX_BCL_VBAT_PK_EST2:case CDC_RX_BCL_VBAT_PK_EST3:case CDC_RX_BCL_VBAT_RF_PROC1:case CDC_RX_BCL_VBAT_RF_PROC2:case CDC_RX_BCL_VBAT_TAC1:case CDC_RX_BCL_VBAT_TAC2:case CDC_RX_BCL_VBAT_TAC3:case CDC_RX_BCL_VBAT_TAC4:case CDC_RX_BCL_VBAT_GAIN_UPD1:case CDC_RX_BCL_VBAT_GAIN_UPD2:case CDC_RX_BCL_VBAT_GAIN_UPD3:case CDC_RX_BCL_VBAT_GAIN_UPD4:case CDC_RX_BCL_VBAT_GAIN_UPD5:case CDC_RX_BCL_VBAT_DEBUG1:case CDC_RX_BCL_VBAT_BAN:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8:case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9:case CDC_RX_BCL_VBAT_ATTN1:case CDC_RX_BCL_VBAT_ATTN2:case CDC_RX_BCL_VBAT_ATTN3:case CDC_RX_BCL_VBAT_DECODE_CTL1:case CDC_RX_BCL_VBAT_DECODE_CTL2:case CDC_RX_BCL_VBAT_DECODE_CFG1:case CDC_RX_BCL_VBAT_DECODE_CFG2:case CDC_RX_BCL_VBAT_DECODE_CFG3:case CDC_RX_BCL_VBAT_DECODE_CFG4:case CDC_RX_INTR_CTRL_CFG:case CDC_RX_INTR_CTRL_PIN1_MASK0:case CDC_RX_INTR_CTRL_PIN2_MASK0:case CDC_RX_INTR_CTRL_LEVEL0:case CDC_RX_INTR_CTRL_BYPASS0:case CDC_RX_INTR_CTRL_SET0:case CDC_RX_RX0_RX_PATH_CTL:case CDC_RX_RX0_RX_PATH_CFG0:case CDC_RX_RX0_RX_PATH_CFG1:case CDC_RX_RX0_RX_PATH_CFG2:case CDC_RX_RX0_RX_PATH_CFG3:case CDC_RX_RX0_RX_VOL_CTL:case CDC_RX_RX0_RX_PATH_MIX_CTL:case CDC_RX_RX0_RX_PATH_MIX_CFG:case CDC_RX_RX0_RX_VOL_MIX_CTL:case CDC_RX_RX0_RX_PATH_SEC1:case CDC_RX_RX0_RX_PATH_SEC2:case CDC_RX_RX0_RX_PATH_SEC3:case CDC_RX_RX0_RX_PATH_SEC4:case CDC_RX_RX0_RX_PATH_SEC7:case CDC_RX_RX0_RX_PATH_MIX_SEC0:case CDC_RX_RX0_RX_PATH_MIX_SEC1:case CDC_RX_RX0_RX_PATH_DSM_CTL:case CDC_RX_RX0_RX_PATH_DSM_DATA1:case CDC_RX_RX0_RX_PATH_DSM_DATA2:case CDC_RX_RX0_RX_PATH_DSM_DATA3:case CDC_RX_RX0_RX_PATH_DSM_DATA4:case CDC_RX_RX0_RX_PATH_DSM_DATA5:case CDC_RX_RX0_RX_PATH_DSM_DATA6:case CDC_RX_IDLE_DETECT_PATH_CTL:case CDC_RX_IDLE_DETECT_CFG0:case CDC_RX_IDLE_DETECT_CFG1:case CDC_RX_IDLE_DETECT_CFG2:case CDC_RX_IDLE_DETECT_CFG3:case CDC_RX_COMPANDER0_CTL0:case CDC_RX_COMPANDER0_CTL1:case CDC_RX_COMPANDER0_CTL2:case CDC_RX_COMPANDER0_CTL3:case CDC_RX_COMPANDER0_CTL4:case CDC_RX_COMPANDER0_CTL5:case CDC_RX_COMPANDER0_CTL7:case CDC_RX_COMPANDER1_CTL0:case CDC_RX_COMPANDER1_CTL1:case CDC_RX_COMPANDER1_CTL2:case CDC_RX_COMPANDER1_CTL3:case CDC_RX_COMPANDER1_CTL4:case CDC_RX_COMPANDER1_CTL5:case CDC_RX_COMPANDER1_CTL7:case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL:case CDC_RX_SIDETONE_IIR0_IIR_CTL:case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL:case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL:case CDC_RX_SIDETONE_IIR1_IIR_CTL:case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL:case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0:case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1:case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2:case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3:case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0:case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1:case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2:case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3:case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL:case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1:case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL:case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1:case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL:case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0:case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL:case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0:case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL:case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0:case CDC_RX_EC_ASRC0_CLK_RST_CTL:case CDC_RX_EC_ASRC0_CTL0:case CDC_RX_EC_ASRC0_CTL1:case CDC_RX_EC_ASRC0_FIFO_CTL:case CDC_RX_EC_ASRC1_CLK_RST_CTL:case CDC_RX_EC_ASRC1_CTL0:case CDC_RX_EC_ASRC1_CTL1:case CDC_RX_EC_ASRC1_FIFO_CTL:case CDC_RX_EC_ASRC2_CLK_RST_CTL:case CDC_RX_EC_ASRC2_CTL0:case CDC_RX_EC_ASRC2_CTL1:case CDC_RX_EC_ASRC2_FIFO_CTL:case CDC_RX_DSD0_PATH_CTL:case CDC_RX_DSD0_CFG0:case CDC_RX_DSD0_CFG1:case CDC_RX_DSD0_CFG2:case CDC_RX_DSD1_PATH_CTL:case CDC_RX_DSD1_CFG0:case CDC_RX_DSD1_CFG1:case CDC_RX_DSD1_CFG2:return true ;switch (rx->codec_version) {case LPASS_CODEC_VERSION_1_0:case LPASS_CODEC_VERSION_1_1:case LPASS_CODEC_VERSION_1_2:case LPASS_CODEC_VERSION_2_0:case LPASS_CODEC_VERSION_2_1:return rx_pre_2_5_is_rw_register(dev, reg);case LPASS_CODEC_VERSION_2_5:case LPASS_CODEC_VERSION_2_6:case LPASS_CODEC_VERSION_2_7:case LPASS_CODEC_VERSION_2_8:return rx_2_5_is_rw_register(dev, reg);default :break ;return false ;static bool rx_is_writeable_register(struct device *dev, unsigned int reg)bool ret;if (!ret)return rx_is_wronly_register(dev, reg);return ret;static bool rx_is_readable_register(struct device *dev, unsigned int reg)switch (reg) {case CDC_RX_TOP_HPHL_COMP_RD_LSB:case CDC_RX_TOP_HPHL_COMP_RD_MSB:case CDC_RX_TOP_HPHR_COMP_RD_LSB:case CDC_RX_TOP_HPHR_COMP_RD_MSB:case CDC_RX_TOP_DSD0_DEBUG_CFG2:case CDC_RX_TOP_DSD1_DEBUG_CFG2:case CDC_RX_BCL_VBAT_GAIN_MON_VAL:case CDC_RX_BCL_VBAT_DECODE_ST:case CDC_RX_INTR_CTRL_PIN1_STATUS0:case CDC_RX_INTR_CTRL_PIN2_STATUS0:case CDC_RX_COMPANDER0_CTL6:case CDC_RX_COMPANDER1_CTL6:case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:case CDC_RX_EC_ASRC0_STATUS_FIFO:case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:case CDC_RX_EC_ASRC1_STATUS_FIFO:case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:case CDC_RX_EC_ASRC2_STATUS_FIFO:return true ;return rx_is_rw_register(dev, reg);static const struct regmap_config rx_regmap_config = {"rx_macro" ,/* 8 but with 32 bit read/write */ static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol)struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);struct rx_macro *rx = snd_soc_component_get_drvdata(component);struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;unsigned short look_ahead_dly_reg;unsigned int val;if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0))else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1))/* Set Look Ahead Delay */ if (val)else /* Set DEM INP Select */ return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);static const struct snd_kcontrol_new rx_int0_dem_inp_mux ="rx_int0_dem_inp" , rx_int0_dem_inp_enum,static const struct snd_kcontrol_new rx_int1_dem_inp_mux ="rx_int1_dem_inp" , rx_int1_dem_inp_enum,static const struct snd_kcontrol_new rx_2_5_int1_dem_inp_mux ="rx_int1_dem_inp" , rx_2_5_int1_dem_inp_enum,static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,int rate_reg_val, u32 sample_rate)struct snd_soc_component *component = dai->component;struct rx_macro *rx = snd_soc_component_get_drvdata(component);/* * Loop through all interpolator MUX inputs and find out * to which interpolator input, the rx port * is connected for (j = 0; j < INTERP_MAX; j++) {if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||/* sample_rate is in Hz */ return 0;static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,int rate_reg_val, u32 sample_rate)struct snd_soc_component *component = dai->component;struct rx_macro *rx = snd_soc_component_get_drvdata(component);for (j = 0; j < INTERP_MAX; j++) {if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {return 0;static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai,int rate_val = 0;int i, ret;for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++)if (sample_rate == sr_val_tbl[i].sample_rate)if (ret)return ret;return ret;static int rx_macro_hw_params(struct snd_pcm_substream *substream,struct snd_pcm_hw_params *params,struct snd_soc_dai *dai)struct snd_soc_component *component = dai->component;struct rx_macro *rx = snd_soc_component_get_drvdata(component);int ret;switch (substream->stream) {case SNDRV_PCM_STREAM_PLAYBACK:if (ret) {
Messung V0.5 C=92 H=97 G=94
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