/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020 MediaTek Inc. * Author: Argus Lin <argus.lin@mediatek.com> #ifndef _MT6359_H_#define _MT6359_H_/*************Register Bit Define*************/ #define MT6359_TOP0_ID 0x0#define MT6359_SMT_CON1 0x32#define MT6359_DRV_CON2 0x3c#define MT6359_DRV_CON3 0x3e#define MT6359_DRV_CON4 0x40#define MT6359_TOP_CKPDN_CON0 0x10c#define MT6359_TOP_CKPDN_CON0_SET 0x10e#define MT6359_TOP_CKPDN_CON0_CLR 0x110#define MT6359_AUXADC_RQST0 0x1108#define MT6359_AUXADC_CON10 0x11a0#define MT6359_AUXADC_ACCDET 0x11ba#define MT6359_LDO_VUSB_OP_EN 0x1d0c#define MT6359_LDO_VUSB_OP_EN_SET 0x1d0e#define MT6359_LDO_VUSB_OP_EN_CLR 0x1d10#define MT6359_AUD_TOP_CKPDN_CON0 0x230c#define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e#define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x2310#define MT6359_AUD_TOP_RST_CON0 0x2320#define MT6359_AUD_TOP_RST_CON0_SET 0x2322#define MT6359_AUD_TOP_RST_CON0_CLR 0x2324#define MT6359_AUD_TOP_INT_CON0 0x2328#define MT6359_AUD_TOP_INT_CON0_SET 0x232a#define MT6359_AUD_TOP_INT_CON0_CLR 0x232c#define MT6359_AUD_TOP_INT_MASK_CON0 0x232e#define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x2330#define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x2332#define MT6359_AUD_TOP_INT_STATUS0 0x2334#define MT6359_AFE_NCP_CFG2 0x24e2#define MT6359_AUDENC_DSN_ID 0x2500#define MT6359_AUDENC_DSN_REV0 0x2502#define MT6359_AUDENC_DSN_DBI 0x2504#define MT6359_AUDENC_DSN_FPI 0x2506#define MT6359_AUDENC_ANA_CON0 0x2508#define MT6359_AUDENC_ANA_CON1 0x250a#define MT6359_AUDENC_ANA_CON2 0x250c#define MT6359_AUDENC_ANA_CON3 0x250e#define MT6359_AUDENC_ANA_CON4 0x2510#define MT6359_AUDENC_ANA_CON5 0x2512#define MT6359_AUDENC_ANA_CON6 0x2514#define MT6359_AUDENC_ANA_CON7 0x2516#define MT6359_AUDENC_ANA_CON8 0x2518#define MT6359_AUDENC_ANA_CON9 0x251a#define MT6359_AUDENC_ANA_CON10 0x251c#define MT6359_AUDENC_ANA_CON11 0x251e#define MT6359_AUDENC_ANA_CON12 0x2520#define MT6359_AUDENC_ANA_CON13 0x2522#define MT6359_AUDENC_ANA_CON14 0x2524#define MT6359_AUDENC_ANA_CON15 0x2526#define MT6359_AUDENC_ANA_CON16 0x2528#define MT6359_AUDENC_ANA_CON17 0x252a#define MT6359_AUDENC_ANA_CON18 0x252c#define MT6359_AUDENC_ANA_CON19 0x252e#define MT6359_AUDENC_ANA_CON20 0x2530#define MT6359_AUDENC_ANA_CON21 0x2532#define MT6359_AUDENC_ANA_CON22 0x2534#define MT6359_AUDENC_ANA_CON23 0x2536#define MT6359_AUDDEC_DSN_ID 0x2580#define MT6359_AUDDEC_DSN_REV0 0x2582#define MT6359_AUDDEC_DSN_DBI 0x2584#define MT6359_AUDDEC_DSN_FPI 0x2586#define MT6359_AUDDEC_ANA_CON0 0x2588#define MT6359_AUDDEC_ANA_CON1 0x258a#define MT6359_AUDDEC_ANA_CON2 0x258c#define MT6359_AUDDEC_ANA_CON3 0x258e#define MT6359_AUDDEC_ANA_CON4 0x2590#define MT6359_AUDDEC_ANA_CON5 0x2592#define MT6359_AUDDEC_ANA_CON6 0x2594#define MT6359_AUDDEC_ANA_CON7 0x2596#define MT6359_AUDDEC_ANA_CON8 0x2598#define MT6359_AUDDEC_ANA_CON9 0x259a#define MT6359_AUDDEC_ANA_CON10 0x259c#define MT6359_AUDDEC_ANA_CON11 0x259e#define MT6359_AUDDEC_ANA_CON12 0x25a0#define MT6359_AUDDEC_ANA_CON13 0x25a2#define MT6359_AUDDEC_ANA_CON14 0x25a4#define MT6359_ACCDET_DSN_DIG_ID 0x2680#define MT6359_ACCDET_DSN_DIG_REV0 0x2682#define MT6359_ACCDET_DSN_DBI 0x2684#define MT6359_ACCDET_DSN_FPI 0x2686#define MT6359_ACCDET_CON0 0x2688#define MT6359_ACCDET_CON1 0x268a#define MT6359_ACCDET_CON2 0x268c#define MT6359_ACCDET_CON3 0x268e#define MT6359_ACCDET_CON4 0x2690#define MT6359_ACCDET_CON5 0x2692#define MT6359_ACCDET_CON6 0x2694#define MT6359_ACCDET_CON7 0x2696#define MT6359_ACCDET_CON8 0x2698#define MT6359_ACCDET_CON9 0x269a#define MT6359_ACCDET_CON10 0x269c#define MT6359_ACCDET_CON11 0x269e#define MT6359_ACCDET_CON12 0x26a0#define MT6359_ACCDET_CON13 0x26a2#define MT6359_ACCDET_CON14 0x26a4#define MT6359_ACCDET_CON15 0x26a6#define MT6359_ACCDET_CON16 0x26a8#define MT6359_ACCDET_CON17 0x26aa#define MT6359_ACCDET_CON18 0x26ac#define MT6359_ACCDET_CON19 0x26ae#define MT6359_ACCDET_CON20 0x26b0#define MT6359_ACCDET_CON21 0x26b2#define MT6359_ACCDET_CON22 0x26b4#define MT6359_ACCDET_CON23 0x26b6#define MT6359_ACCDET_CON24 0x26b8#define MT6359_ACCDET_CON25 0x26ba#define MT6359_ACCDET_CON26 0x26bc#define MT6359_ACCDET_CON27 0x26be#define MT6359_ACCDET_CON28 0x26c0#define MT6359_ACCDET_CON29 0x26c2#define MT6359_ACCDET_CON30 0x26c4#define MT6359_ACCDET_CON31 0x26c6#define MT6359_ACCDET_CON32 0x26c8#define MT6359_ACCDET_CON33 0x26ca#define MT6359_ACCDET_CON34 0x26cc#define MT6359_ACCDET_CON35 0x26ce#define MT6359_ACCDET_CON36 0x26d0#define MT6359_ACCDET_CON37 0x26d2#define MT6359_ACCDET_CON38 0x26d4#define MT6359_ACCDET_CON39 0x26d6#define MT6359_ACCDET_CON40 0x26d8#define TOP0_ANA_ID_ADDR \#define TOP0_ANA_ID_SFT 0#define TOP0_ANA_ID_MASK 0xFF#define TOP0_ANA_ID_MASK_SFT (0xFF << 0)#define AUXADC_RQST_CH0_ADDR \#define AUXADC_RQST_CH0_SFT 0#define AUXADC_RQST_CH0_MASK 0x1#define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)#define AUXADC_ACCDET_ANASWCTRL_EN_ADDR \#define AUXADC_ACCDET_ANASWCTRL_EN_SFT 6#define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1#define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)#define AUXADC_ACCDET_AUTO_SPL_ADDR \#define AUXADC_ACCDET_AUTO_SPL_SFT 0#define AUXADC_ACCDET_AUTO_SPL_MASK 0x1#define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)#define AUXADC_ACCDET_AUTO_RQST_CLR_ADDR \#define AUXADC_ACCDET_AUTO_RQST_CLR_SFT 1#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)#define AUXADC_ACCDET_DIG1_RSV0_ADDR \#define AUXADC_ACCDET_DIG1_RSV0_SFT 2#define AUXADC_ACCDET_DIG1_RSV0_MASK 0x3F#define AUXADC_ACCDET_DIG1_RSV0_MASK_SFT (0x3F << 2)#define AUXADC_ACCDET_DIG0_RSV0_ADDR \#define AUXADC_ACCDET_DIG0_RSV0_SFT 8#define AUXADC_ACCDET_DIG0_RSV0_MASK 0xFF#define AUXADC_ACCDET_DIG0_RSV0_MASK_SFT (0xFF << 8)#define RG_ACCDET_CK_PDN_ADDR \#define RG_ACCDET_CK_PDN_SFT 0#define RG_ACCDET_CK_PDN_MASK 0x1#define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)#define RG_ACCDET_RST_ADDR \#define RG_ACCDET_RST_SFT 1#define RG_ACCDET_RST_MASK 0x1#define RG_ACCDET_RST_MASK_SFT (0x1 << 1)#define BANK_ACCDET_SWRST_ADDR \#define BANK_ACCDET_SWRST_SFT 0#define BANK_ACCDET_SWRST_MASK 0x1#define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)#define RG_INT_EN_ACCDET_ADDR \#define RG_INT_EN_ACCDET_SFT 5#define RG_INT_EN_ACCDET_MASK 0x1#define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)#define RG_INT_EN_ACCDET_EINT0_ADDR \#define RG_INT_EN_ACCDET_EINT0_SFT 6#define RG_INT_EN_ACCDET_EINT0_MASK 0x1#define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)#define RG_INT_EN_ACCDET_EINT1_ADDR \#define RG_INT_EN_ACCDET_EINT1_SFT 7#define RG_INT_EN_ACCDET_EINT1_MASK 0x1#define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)#define RG_INT_MASK_ACCDET_ADDR \#define RG_INT_MASK_ACCDET_SFT 5#define RG_INT_MASK_ACCDET_MASK 0x1#define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)#define RG_INT_MASK_ACCDET_EINT0_ADDR \#define RG_INT_MASK_ACCDET_EINT0_SFT 6#define RG_INT_MASK_ACCDET_EINT0_MASK 0x1#define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)#define RG_INT_MASK_ACCDET_EINT1_ADDR \#define RG_INT_MASK_ACCDET_EINT1_SFT 7#define RG_INT_MASK_ACCDET_EINT1_MASK 0x1#define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)#define RG_INT_STATUS_ACCDET_ADDR \#define RG_INT_STATUS_ACCDET_SFT 5#define RG_INT_STATUS_ACCDET_MASK 0x1#define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)#define RG_INT_STATUS_ACCDET_EINT0_ADDR \#define RG_INT_STATUS_ACCDET_EINT0_SFT 6#define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1#define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)#define RG_INT_STATUS_ACCDET_EINT1_ADDR \#define RG_INT_STATUS_ACCDET_EINT1_SFT 7#define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1#define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)#define RG_INT_RAW_STATUS_ACCDET_ADDR \#define RG_INT_RAW_STATUS_ACCDET_SFT 5#define RG_INT_RAW_STATUS_ACCDET_MASK 0x1#define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)#define RG_INT_RAW_STATUS_ACCDET_EINT0_ADDR \#define RG_INT_RAW_STATUS_ACCDET_EINT0_SFT 6#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)#define RG_INT_RAW_STATUS_ACCDET_EINT1_ADDR \#define RG_INT_RAW_STATUS_ACCDET_EINT1_SFT 7#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)#define RG_AUDACCDETMICBIAS0PULLLOW_ADDR \#define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0#define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1#define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)#define RG_AUDACCDETMICBIAS1PULLLOW_ADDR \#define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1#define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1#define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)#define RG_AUDACCDETMICBIAS2PULLLOW_ADDR \#define RG_AUDACCDETMICBIAS2PULLLOW_SFT 2#define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1#define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)#define RG_AUDACCDETVIN1PULLLOW_ADDR \#define RG_AUDACCDETVIN1PULLLOW_SFT 3#define RG_AUDACCDETVIN1PULLLOW_MASK 0x1#define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)#define RG_AUDACCDETVTHACAL_ADDR \#define RG_AUDACCDETVTHACAL_SFT 4#define RG_AUDACCDETVTHACAL_MASK 0x1#define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)#define RG_AUDACCDETVTHBCAL_ADDR \#define RG_AUDACCDETVTHBCAL_SFT 5#define RG_AUDACCDETVTHBCAL_MASK 0x1#define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)#define RG_AUDACCDETTVDET_ADDR \#define RG_AUDACCDETTVDET_SFT 6#define RG_AUDACCDETTVDET_MASK 0x1#define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)#define RG_ACCDETSEL_ADDR \#define RG_ACCDETSEL_SFT 7#define RG_ACCDETSEL_MASK 0x1#define RG_ACCDETSEL_MASK_SFT (0x1 << 7)#define RG_AUDPWDBMICBIAS1_ADDR \#define RG_AUDPWDBMICBIAS1_SFT 0#define RG_AUDPWDBMICBIAS1_MASK 0x1#define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)#define RG_AUDMICBIAS1BYPASSEN_ADDR \#define RG_AUDMICBIAS1BYPASSEN_SFT 1#define RG_AUDMICBIAS1BYPASSEN_MASK 0x1#define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)#define RG_AUDMICBIAS1LOWPEN_ADDR \#define RG_AUDMICBIAS1LOWPEN_SFT 2#define RG_AUDMICBIAS1LOWPEN_MASK 0x1#define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)#define RG_AUDMICBIAS1VREF_ADDR \#define RG_AUDMICBIAS1VREF_SFT 4#define RG_AUDMICBIAS1VREF_MASK 0x7#define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)#define RG_AUDMICBIAS1DCSW1PEN_ADDR \#define RG_AUDMICBIAS1DCSW1PEN_SFT 8#define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1#define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)#define RG_AUDMICBIAS1DCSW1NEN_ADDR \#define RG_AUDMICBIAS1DCSW1NEN_SFT 9#define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1#define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)#define RG_BANDGAPGEN_ADDR \#define RG_BANDGAPGEN_SFT 10#define RG_BANDGAPGEN_MASK 0x1#define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)#define RG_AUDMICBIAS1HVEN_ADDR \#define RG_AUDMICBIAS1HVEN_SFT 12#define RG_AUDMICBIAS1HVEN_MASK 0x1#define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)#define RG_AUDMICBIAS1HVVREF_ADDR \#define RG_AUDMICBIAS1HVVREF_SFT 13#define RG_AUDMICBIAS1HVVREF_MASK 0x1#define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)#define RG_EINT0NOHYS_ADDR \#define RG_EINT0NOHYS_SFT 10#define RG_EINT0NOHYS_MASK 0x1#define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)#define RG_EINT0CONFIGACCDET_ADDR \#define RG_EINT0CONFIGACCDET_SFT 11#define RG_EINT0CONFIGACCDET_MASK 0x1#define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)#define RG_EINT0HIRENB_ADDR \#define RG_EINT0HIRENB_SFT 12#define RG_EINT0HIRENB_MASK 0x1#define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)#define RG_ACCDET2AUXRESBYPASS_ADDR \#define RG_ACCDET2AUXRESBYPASS_SFT 13#define RG_ACCDET2AUXRESBYPASS_MASK 0x1#define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)#define RG_ACCDET2AUXSWEN_ADDR \#define RG_ACCDET2AUXSWEN_SFT 14#define RG_ACCDET2AUXSWEN_MASK 0x1#define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)#define RG_AUDACCDETMICBIAS3PULLLOW_ADDR \#define RG_AUDACCDETMICBIAS3PULLLOW_SFT 15#define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1#define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)#define RG_EINT1CONFIGACCDET_ADDR \#define RG_EINT1CONFIGACCDET_SFT 0#define RG_EINT1CONFIGACCDET_MASK 0x1#define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)#define RG_EINT1HIRENB_ADDR \#define RG_EINT1HIRENB_SFT 1#define RG_EINT1HIRENB_MASK 0x1#define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)#define RG_EINT1NOHYS_ADDR \#define RG_EINT1NOHYS_SFT 2#define RG_EINT1NOHYS_MASK 0x1#define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)#define RG_EINTCOMPVTH_ADDR \#define RG_MTEST_EN_ADDR \#define RG_MTEST_EN_SFT 8#define RG_MTEST_EN_MASK 0x1#define RG_MTEST_EN_MASK_SFT (0x1 << 8)#define RG_MTEST_SEL_ADDR \#define RG_MTEST_SEL_SFT 9#define RG_MTEST_SEL_MASK 0x1#define RG_MTEST_SEL_MASK_SFT (0x1 << 9)#define RG_MTEST_CURRENT_ADDR \#define RG_MTEST_CURRENT_SFT 10#define RG_MTEST_CURRENT_MASK 0x1#define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)#define RG_ANALOGFDEN_ADDR \#define RG_ANALOGFDEN_SFT 12#define RG_ANALOGFDEN_MASK 0x1#define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)#define RG_FDVIN1PPULLLOW_ADDR \#define RG_FDVIN1PPULLLOW_SFT 13#define RG_FDVIN1PPULLLOW_MASK 0x1#define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)#define RG_FDEINT0TYPE_ADDR \#define RG_FDEINT0TYPE_SFT 14#define RG_FDEINT0TYPE_MASK 0x1#define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)#define RG_FDEINT1TYPE_ADDR \#define RG_FDEINT1TYPE_SFT 15#define RG_FDEINT1TYPE_MASK 0x1#define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)#define RG_EINT0CMPEN_ADDR \#define RG_EINT0CMPEN_SFT 0#define RG_EINT0CMPEN_MASK 0x1#define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)#define RG_EINT0CMPMEN_ADDR \#define RG_EINT0CMPMEN_SFT 1#define RG_EINT0CMPMEN_MASK 0x1#define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)#define RG_EINT0EN_ADDR \#define RG_EINT0EN_SFT 2#define RG_EINT0EN_MASK 0x1#define RG_EINT0EN_MASK_SFT (0x1 << 2)#define RG_EINT0CEN_ADDR \#define RG_EINT0CEN_SFT 3#define RG_EINT0CEN_MASK 0x1#define RG_EINT0CEN_MASK_SFT (0x1 << 3)#define RG_EINT0INVEN_ADDR \#define RG_EINT0INVEN_SFT 4#define RG_EINT0INVEN_MASK 0x1#define RG_EINT0INVEN_MASK_SFT (0x1 << 4)#define RG_EINT0CTURBO_ADDR \#define RG_EINT0CTURBO_SFT 5#define RG_EINT0CTURBO_MASK 0x7#define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)#define RG_EINT1CMPEN_ADDR \#define RG_EINT1CMPEN_SFT 8#define RG_EINT1CMPEN_MASK 0x1#define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)#define RG_EINT1CMPMEN_ADDR \#define RG_EINT1CMPMEN_SFT 9#define RG_EINT1CMPMEN_MASK 0x1#define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)#define RG_EINT1EN_ADDR \#define RG_EINT1EN_SFT 10#define RG_EINT1EN_MASK 0x1#define RG_EINT1EN_MASK_SFT (0x1 << 10)#define RG_EINT1CEN_ADDR \#define RG_EINT1CEN_SFT 11#define RG_EINT1CEN_MASK 0x1#define RG_EINT1CEN_MASK_SFT (0x1 << 11)#define RG_EINT1INVEN_ADDR \#define RG_EINT1INVEN_SFT 12#define RG_EINT1INVEN_MASK 0x1#define RG_EINT1INVEN_MASK_SFT (0x1 << 12)#define RG_EINT1CTURBO_ADDR \#define RG_EINT1CTURBO_SFT 13#define RG_EINT1CTURBO_MASK 0x7#define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)#define RG_ACCDETSPARE_ADDR \#define ACCDET_ANA_ID_ADDR \#define ACCDET_ANA_ID_SFT 0#define ACCDET_ANA_ID_MASK 0xFF#define ACCDET_ANA_ID_MASK_SFT (0xFF << 0)#define ACCDET_DIG_ID_ADDR \#define ACCDET_DIG_ID_SFT 8#define ACCDET_DIG_ID_MASK 0xFF#define ACCDET_DIG_ID_MASK_SFT (0xFF << 8)#define ACCDET_ANA_MINOR_REV_ADDR \#define ACCDET_ANA_MINOR_REV_SFT 0#define ACCDET_ANA_MINOR_REV_MASK 0xF#define ACCDET_ANA_MINOR_REV_MASK_SFT (0xF << 0)#define ACCDET_ANA_MAJOR_REV_ADDR \#define ACCDET_ANA_MAJOR_REV_SFT 4#define ACCDET_ANA_MAJOR_REV_MASK 0xF#define ACCDET_ANA_MAJOR_REV_MASK_SFT (0xF << 4)#define ACCDET_DIG_MINOR_REV_ADDR \#define ACCDET_DIG_MINOR_REV_SFT 8#define ACCDET_DIG_MINOR_REV_MASK 0xF#define ACCDET_DIG_MINOR_REV_MASK_SFT (0xF << 8)#define ACCDET_DIG_MAJOR_REV_ADDR \#define ACCDET_DIG_MAJOR_REV_SFT 12#define ACCDET_DIG_MAJOR_REV_MASK 0xF#define ACCDET_DIG_MAJOR_REV_MASK_SFT (0xF << 12)#define ACCDET_DSN_CBS_ADDR \#define ACCDET_DSN_CBS_SFT 0#define ACCDET_DSN_CBS_MASK 0x3#define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)#define ACCDET_DSN_BIX_ADDR \#define ACCDET_DSN_BIX_SFT 2#define ACCDET_DSN_BIX_MASK 0x3#define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2)#define ACCDET_ESP_ADDR \#define ACCDET_ESP_SFT 8#define ACCDET_ESP_MASK 0xFF#define ACCDET_ESP_MASK_SFT (0xFF << 8)#define ACCDET_DSN_FPI_ADDR \#define ACCDET_DSN_FPI_SFT 0#define ACCDET_DSN_FPI_MASK 0xFF#define ACCDET_DSN_FPI_MASK_SFT (0xFF << 0)#define ACCDET_AUXADC_SEL_ADDR \#define ACCDET_AUXADC_SEL_SFT 0#define ACCDET_AUXADC_SEL_MASK 0x1#define ACCDET_AUXADC_SEL_MASK_SFT (0x1 << 0)#define ACCDET_AUXADC_SW_ADDR \#define ACCDET_AUXADC_SW_SFT 1#define ACCDET_AUXADC_SW_MASK 0x1#define ACCDET_AUXADC_SW_MASK_SFT (0x1 << 1)#define ACCDET_TEST_AUXADC_ADDR \#define ACCDET_TEST_AUXADC_SFT 2#define ACCDET_TEST_AUXADC_MASK 0x1#define ACCDET_TEST_AUXADC_MASK_SFT (0x1 << 2)#define ACCDET_AUXADC_ANASWCTRL_SEL_ADDR \#define ACCDET_AUXADC_ANASWCTRL_SEL_SFT 8#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK 0x1#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK_SFT (0x1 << 8)#define AUDACCDETAUXADCSWCTRL_SEL_ADDR \#define AUDACCDETAUXADCSWCTRL_SEL_SFT 9#define AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1#define AUDACCDETAUXADCSWCTRL_SEL_MASK_SFT (0x1 << 9)#define AUDACCDETAUXADCSWCTRL_SW_ADDR \#define AUDACCDETAUXADCSWCTRL_SW_SFT 10#define AUDACCDETAUXADCSWCTRL_SW_MASK 0x1#define AUDACCDETAUXADCSWCTRL_SW_MASK_SFT (0x1 << 10)#define ACCDET_TEST_ANA_ADDR \#define ACCDET_TEST_ANA_SFT 11#define ACCDET_TEST_ANA_MASK 0x1#define ACCDET_TEST_ANA_MASK_SFT (0x1 << 11)#define RG_AUDACCDETRSV_ADDR \#define RG_AUDACCDETRSV_SFT 13#define RG_AUDACCDETRSV_MASK 0x3#define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13)#define ACCDET_SW_EN_ADDR \#define ACCDET_SW_EN_SFT 0#define ACCDET_SW_EN_MASK 0x1#define ACCDET_SW_EN_MASK_SFT (0x1 << 0)#define ACCDET_SEQ_INIT_ADDR \#define ACCDET_SEQ_INIT_SFT 1#define ACCDET_SEQ_INIT_MASK 0x1#define ACCDET_SEQ_INIT_MASK_SFT (0x1 << 1)#define ACCDET_EINT0_SW_EN_ADDR \#define ACCDET_EINT0_SW_EN_SFT 2#define ACCDET_EINT0_SW_EN_MASK 0x1#define ACCDET_EINT0_SW_EN_MASK_SFT (0x1 << 2)#define ACCDET_EINT0_SEQ_INIT_ADDR \#define ACCDET_EINT0_SEQ_INIT_SFT 3#define ACCDET_EINT0_SEQ_INIT_MASK 0x1#define ACCDET_EINT0_SEQ_INIT_MASK_SFT (0x1 << 3)#define ACCDET_EINT1_SW_EN_ADDR \#define ACCDET_EINT1_SW_EN_SFT 4#define ACCDET_EINT1_SW_EN_MASK 0x1#define ACCDET_EINT1_SW_EN_MASK_SFT (0x1 << 4)#define ACCDET_EINT1_SEQ_INIT_ADDR \#define ACCDET_EINT1_SEQ_INIT_SFT 5#define ACCDET_EINT1_SEQ_INIT_MASK 0x1#define ACCDET_EINT1_SEQ_INIT_MASK_SFT (0x1 << 5)#define ACCDET_EINT0_INVERTER_SW_EN_ADDR \#define ACCDET_EINT0_INVERTER_SW_EN_SFT 6#define ACCDET_EINT0_INVERTER_SW_EN_MASK 0x1#define ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT (0x1 << 6)#define ACCDET_EINT0_INVERTER_SEQ_INIT_ADDR \#define ACCDET_EINT0_INVERTER_SEQ_INIT_SFT 7#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK 0x1#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 7)#define ACCDET_EINT1_INVERTER_SW_EN_ADDR \#define ACCDET_EINT1_INVERTER_SW_EN_SFT 8#define ACCDET_EINT1_INVERTER_SW_EN_MASK 0x1#define ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT (0x1 << 8)#define ACCDET_EINT1_INVERTER_SEQ_INIT_ADDR \#define ACCDET_EINT1_INVERTER_SEQ_INIT_SFT 9#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK 0x1#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 9)#define ACCDET_EINT0_M_SW_EN_ADDR \#define ACCDET_EINT0_M_SW_EN_SFT 10#define ACCDET_EINT0_M_SW_EN_MASK 0x1#define ACCDET_EINT0_M_SW_EN_MASK_SFT (0x1 << 10)#define ACCDET_EINT1_M_SW_EN_ADDR \#define ACCDET_EINT1_M_SW_EN_SFT 11#define ACCDET_EINT1_M_SW_EN_MASK 0x1#define ACCDET_EINT1_M_SW_EN_MASK_SFT (0x1 << 11)#define ACCDET_EINT_M_DETECT_EN_ADDR \#define ACCDET_EINT_M_DETECT_EN_SFT 12#define ACCDET_EINT_M_DETECT_EN_MASK 0x1#define ACCDET_EINT_M_DETECT_EN_MASK_SFT (0x1 << 12)#define ACCDET_CMP_PWM_EN_ADDR \#define ACCDET_CMP_PWM_EN_SFT 0#define ACCDET_CMP_PWM_EN_MASK 0x1#define ACCDET_CMP_PWM_EN_MASK_SFT (0x1 << 0)#define ACCDET_VTH_PWM_EN_ADDR \#define ACCDET_VTH_PWM_EN_SFT 1#define ACCDET_VTH_PWM_EN_MASK 0x1#define ACCDET_VTH_PWM_EN_MASK_SFT (0x1 << 1)#define ACCDET_MBIAS_PWM_EN_ADDR \#define ACCDET_MBIAS_PWM_EN_SFT 2#define ACCDET_MBIAS_PWM_EN_MASK 0x1#define ACCDET_MBIAS_PWM_EN_MASK_SFT (0x1 << 2)#define ACCDET_EINT_EN_PWM_EN_ADDR \#define ACCDET_EINT_EN_PWM_EN_SFT 3#define ACCDET_EINT_EN_PWM_EN_MASK 0x1#define ACCDET_EINT_EN_PWM_EN_MASK_SFT (0x1 << 3)#define ACCDET_EINT_CMPEN_PWM_EN_ADDR \#define ACCDET_EINT_CMPEN_PWM_EN_SFT 4#define ACCDET_EINT_CMPEN_PWM_EN_MASK 0x1#define ACCDET_EINT_CMPEN_PWM_EN_MASK_SFT (0x1 << 4)#define ACCDET_EINT_CMPMEN_PWM_EN_ADDR \#define ACCDET_EINT_CMPMEN_PWM_EN_SFT 5#define ACCDET_EINT_CMPMEN_PWM_EN_MASK 0x1#define ACCDET_EINT_CMPMEN_PWM_EN_MASK_SFT (0x1 << 5)#define ACCDET_EINT_CTURBO_PWM_EN_ADDR \#define ACCDET_EINT_CTURBO_PWM_EN_SFT 6#define ACCDET_EINT_CTURBO_PWM_EN_MASK 0x1#define ACCDET_EINT_CTURBO_PWM_EN_MASK_SFT (0x1 << 6)#define ACCDET_CMP_PWM_IDLE_ADDR \#define ACCDET_CMP_PWM_IDLE_SFT 8#define ACCDET_CMP_PWM_IDLE_MASK 0x1#define ACCDET_CMP_PWM_IDLE_MASK_SFT (0x1 << 8)#define ACCDET_VTH_PWM_IDLE_ADDR \#define ACCDET_VTH_PWM_IDLE_SFT 9#define ACCDET_VTH_PWM_IDLE_MASK 0x1#define ACCDET_VTH_PWM_IDLE_MASK_SFT (0x1 << 9)#define ACCDET_MBIAS_PWM_IDLE_ADDR \#define ACCDET_MBIAS_PWM_IDLE_SFT 10#define ACCDET_MBIAS_PWM_IDLE_MASK 0x1#define ACCDET_MBIAS_PWM_IDLE_MASK_SFT (0x1 << 10)#define ACCDET_EINT0_CMPEN_PWM_IDLE_ADDR \#define ACCDET_EINT0_CMPEN_PWM_IDLE_SFT 11#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK 0x1#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 11)#define ACCDET_EINT1_CMPEN_PWM_IDLE_ADDR \#define ACCDET_EINT1_CMPEN_PWM_IDLE_SFT 12#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK 0x1#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 12)#define ACCDET_PWM_EN_SW_ADDR \#define ACCDET_PWM_EN_SW_SFT 13#define ACCDET_PWM_EN_SW_MASK 0x1#define ACCDET_PWM_EN_SW_MASK_SFT (0x1 << 13)#define ACCDET_PWM_EN_SEL_ADDR \#define ACCDET_PWM_EN_SEL_SFT 14#define ACCDET_PWM_EN_SEL_MASK 0x3#define ACCDET_PWM_EN_SEL_MASK_SFT (0x3 << 14)#define ACCDET_PWM_WIDTH_ADDR \#define ACCDET_PWM_WIDTH_SFT 0#define ACCDET_PWM_WIDTH_MASK 0xFFFF#define ACCDET_PWM_WIDTH_MASK_SFT (0xFFFF << 0)#define ACCDET_PWM_THRESH_ADDR \#define ACCDET_PWM_THRESH_SFT 0#define ACCDET_PWM_THRESH_MASK 0xFFFF#define ACCDET_PWM_THRESH_MASK_SFT (0xFFFF << 0)#define ACCDET_RISE_DELAY_ADDR \#define ACCDET_RISE_DELAY_SFT 0#define ACCDET_RISE_DELAY_MASK 0x7FFF#define ACCDET_RISE_DELAY_MASK_SFT (0x7FFF << 0)#define ACCDET_FALL_DELAY_ADDR \#define ACCDET_FALL_DELAY_SFT 15#define ACCDET_FALL_DELAY_MASK 0x1#define ACCDET_FALL_DELAY_MASK_SFT (0x1 << 15)#define ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR \#define ACCDET_EINT_CMPMEN_PWM_THRESH_SFT 0#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK 0x7#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK_SFT (0x7 << 0)#define ACCDET_EINT_CMPMEN_PWM_WIDTH_ADDR \#define ACCDET_EINT_CMPMEN_PWM_WIDTH_SFT 4#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK 0x7#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK_SFT (0x7 << 4)#define ACCDET_EINT_EN_PWM_THRESH_ADDR \#define ACCDET_EINT_EN_PWM_THRESH_SFT 0#define ACCDET_EINT_EN_PWM_THRESH_MASK 0x7#define ACCDET_EINT_EN_PWM_THRESH_MASK_SFT (0x7 << 0)#define ACCDET_EINT_EN_PWM_WIDTH_ADDR \#define ACCDET_EINT_EN_PWM_WIDTH_SFT 4#define ACCDET_EINT_EN_PWM_WIDTH_MASK 0x3#define ACCDET_EINT_EN_PWM_WIDTH_MASK_SFT (0x3 << 4)#define ACCDET_EINT_CMPEN_PWM_THRESH_ADDR \#define ACCDET_EINT_CMPEN_PWM_THRESH_SFT 8#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK 0x7#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK_SFT (0x7 << 8)#define ACCDET_EINT_CMPEN_PWM_WIDTH_ADDR \#define ACCDET_EINT_CMPEN_PWM_WIDTH_SFT 12#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK 0x3#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK_SFT (0x3 << 12)#define ACCDET_DEBOUNCE0_ADDR \#define ACCDET_DEBOUNCE0_SFT 0#define ACCDET_DEBOUNCE0_MASK 0xFFFF#define ACCDET_DEBOUNCE0_MASK_SFT (0xFFFF << 0)#define ACCDET_DEBOUNCE1_ADDR \#define ACCDET_DEBOUNCE1_SFT 0#define ACCDET_DEBOUNCE1_MASK 0xFFFF#define ACCDET_DEBOUNCE1_MASK_SFT (0xFFFF << 0)#define ACCDET_DEBOUNCE2_ADDR \#define ACCDET_DEBOUNCE2_SFT 0#define ACCDET_DEBOUNCE2_MASK 0xFFFF#define ACCDET_DEBOUNCE2_MASK_SFT (0xFFFF << 0)#define ACCDET_DEBOUNCE3_ADDR \#define ACCDET_DEBOUNCE3_SFT 0#define ACCDET_DEBOUNCE3_MASK 0xFFFF#define ACCDET_DEBOUNCE3_MASK_SFT (0xFFFF << 0)#define ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR \#define ACCDET_CONNECT_AUXADC_TIME_DIG_SFT 0#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK 0xFFFF#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK_SFT (0xFFFF << 0)#define ACCDET_CONNECT_AUXADC_TIME_ANA_ADDR \#define ACCDET_CONNECT_AUXADC_TIME_ANA_SFT 0#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK 0xFFFF#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK_SFT (0xFFFF << 0)#define ACCDET_EINT_DEBOUNCE0_ADDR \#define ACCDET_EINT_DEBOUNCE0_SFT 0#define ACCDET_EINT_DEBOUNCE0_MASK 0xF#define ACCDET_EINT_DEBOUNCE0_MASK_SFT (0xF << 0)#define ACCDET_EINT_DEBOUNCE1_ADDR \#define ACCDET_EINT_DEBOUNCE1_SFT 4#define ACCDET_EINT_DEBOUNCE1_MASK 0xF#define ACCDET_EINT_DEBOUNCE1_MASK_SFT (0xF << 4)#define ACCDET_EINT_DEBOUNCE2_ADDR \#define ACCDET_EINT_DEBOUNCE2_SFT 8#define ACCDET_EINT_DEBOUNCE2_MASK 0xF#define ACCDET_EINT_DEBOUNCE2_MASK_SFT (0xF << 8)#define ACCDET_EINT_DEBOUNCE3_ADDR \#define ACCDET_EINT_DEBOUNCE3_SFT 12#define ACCDET_EINT_DEBOUNCE3_MASK 0xF#define ACCDET_EINT_DEBOUNCE3_MASK_SFT (0xF << 12)#define ACCDET_EINT_INVERTER_DEBOUNCE_ADDR \#define ACCDET_EINT_INVERTER_DEBOUNCE_SFT 0#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK 0xF#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK_SFT (0xF << 0)#define ACCDET_IVAL_CUR_IN_ADDR \#define ACCDET_IVAL_CUR_IN_SFT 0#define ACCDET_IVAL_CUR_IN_MASK 0x3#define ACCDET_IVAL_CUR_IN_MASK_SFT (0x3 << 0)#define ACCDET_IVAL_SAM_IN_ADDR \#define ACCDET_IVAL_SAM_IN_SFT 2#define ACCDET_IVAL_SAM_IN_MASK 0x3#define ACCDET_IVAL_SAM_IN_MASK_SFT (0x3 << 2)#define ACCDET_IVAL_MEM_IN_ADDR \#define ACCDET_IVAL_MEM_IN_SFT 4#define ACCDET_IVAL_MEM_IN_MASK 0x3#define ACCDET_IVAL_MEM_IN_MASK_SFT (0x3 << 4)#define ACCDET_EINT_IVAL_CUR_IN_ADDR \#define ACCDET_EINT_IVAL_CUR_IN_SFT 6#define ACCDET_EINT_IVAL_CUR_IN_MASK 0x3#define ACCDET_EINT_IVAL_CUR_IN_MASK_SFT (0x3 << 6)#define ACCDET_EINT_IVAL_SAM_IN_ADDR \#define ACCDET_EINT_IVAL_SAM_IN_SFT 8#define ACCDET_EINT_IVAL_SAM_IN_MASK 0x3#define ACCDET_EINT_IVAL_SAM_IN_MASK_SFT (0x3 << 8)#define ACCDET_EINT_IVAL_MEM_IN_ADDR \#define ACCDET_EINT_IVAL_MEM_IN_SFT 10#define ACCDET_EINT_IVAL_MEM_IN_MASK 0x3#define ACCDET_EINT_IVAL_MEM_IN_MASK_SFT (0x3 << 10)#define ACCDET_IVAL_SEL_ADDR \#define ACCDET_IVAL_SEL_SFT 12#define ACCDET_IVAL_SEL_MASK 0x1#define ACCDET_IVAL_SEL_MASK_SFT (0x1 << 12)#define ACCDET_EINT_IVAL_SEL_ADDR \#define ACCDET_EINT_IVAL_SEL_SFT 13#define ACCDET_EINT_IVAL_SEL_MASK 0x1#define ACCDET_EINT_IVAL_SEL_MASK_SFT (0x1 << 13)#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_ADDR \#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_SFT 0#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK 0x1#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK_SFT (0x1 << 0)#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_ADDR \#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_SFT 1#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK 0x1#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK_SFT (0x1 << 1)#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_ADDR \#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_SFT 2#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK 0x1#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK_SFT (0x1 << 2)#define ACCDET_EINT_INVERTER_IVAL_SEL_ADDR \#define ACCDET_EINT_INVERTER_IVAL_SEL_SFT 3#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK 0x1#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT (0x1 << 3)#define ACCDET_IRQ_ADDR \#define ACCDET_IRQ_SFT 0#define ACCDET_IRQ_MASK 0x1#define ACCDET_IRQ_MASK_SFT (0x1 << 0)#define ACCDET_EINT0_IRQ_ADDR \#define ACCDET_EINT0_IRQ_SFT 2#define ACCDET_EINT0_IRQ_MASK 0x1#define ACCDET_EINT0_IRQ_MASK_SFT (0x1 << 2)#define ACCDET_EINT1_IRQ_ADDR \#define ACCDET_EINT1_IRQ_SFT 3#define ACCDET_EINT1_IRQ_MASK 0x1#define ACCDET_EINT1_IRQ_MASK_SFT (0x1 << 3)#define ACCDET_EINT_IN_INVERSE_ADDR \#define ACCDET_EINT_IN_INVERSE_SFT 4#define ACCDET_EINT_IN_INVERSE_MASK 0x1#define ACCDET_EINT_IN_INVERSE_MASK_SFT (0x1 << 4)#define ACCDET_IRQ_CLR_ADDR \#define ACCDET_IRQ_CLR_SFT 8#define ACCDET_IRQ_CLR_MASK 0x1#define ACCDET_IRQ_CLR_MASK_SFT (0x1 << 8)#define ACCDET_EINT0_IRQ_CLR_ADDR \#define ACCDET_EINT0_IRQ_CLR_SFT 10#define ACCDET_EINT0_IRQ_CLR_MASK 0x1#define ACCDET_EINT0_IRQ_CLR_MASK_SFT (0x1 << 10)#define ACCDET_EINT1_IRQ_CLR_ADDR \#define ACCDET_EINT1_IRQ_CLR_SFT 11#define ACCDET_EINT1_IRQ_CLR_MASK 0x1#define ACCDET_EINT1_IRQ_CLR_MASK_SFT (0x1 << 11)#define ACCDET_EINT_M_PLUG_IN_NUM_ADDR \#define ACCDET_EINT_M_PLUG_IN_NUM_SFT 12#define ACCDET_EINT_M_PLUG_IN_NUM_MASK 0x7#define ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT (0x7 << 12)#define ACCDET_DA_STABLE_ADDR \#define ACCDET_DA_STABLE_SFT 0#define ACCDET_DA_STABLE_MASK 0x1#define ACCDET_DA_STABLE_MASK_SFT (0x1 << 0)#define ACCDET_EINT0_EN_STABLE_ADDR \#define ACCDET_EINT0_EN_STABLE_SFT 1#define ACCDET_EINT0_EN_STABLE_MASK 0x1#define ACCDET_EINT0_EN_STABLE_MASK_SFT (0x1 << 1)#define ACCDET_EINT0_CMPEN_STABLE_ADDR \#define ACCDET_EINT0_CMPEN_STABLE_SFT 2#define ACCDET_EINT0_CMPEN_STABLE_MASK 0x1#define ACCDET_EINT0_CMPEN_STABLE_MASK_SFT (0x1 << 2)#define ACCDET_EINT0_CMPMEN_STABLE_ADDR \#define ACCDET_EINT0_CMPMEN_STABLE_SFT 3#define ACCDET_EINT0_CMPMEN_STABLE_MASK 0x1#define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT (0x1 << 3)#define ACCDET_EINT0_CTURBO_STABLE_ADDR \#define ACCDET_EINT0_CTURBO_STABLE_SFT 4#define ACCDET_EINT0_CTURBO_STABLE_MASK 0x1#define ACCDET_EINT0_CTURBO_STABLE_MASK_SFT (0x1 << 4)#define ACCDET_EINT0_CEN_STABLE_ADDR \#define ACCDET_EINT0_CEN_STABLE_SFT 5#define ACCDET_EINT0_CEN_STABLE_MASK 0x1#define ACCDET_EINT0_CEN_STABLE_MASK_SFT (0x1 << 5)#define ACCDET_EINT1_EN_STABLE_ADDR \#define ACCDET_EINT1_EN_STABLE_SFT 6#define ACCDET_EINT1_EN_STABLE_MASK 0x1#define ACCDET_EINT1_EN_STABLE_MASK_SFT (0x1 << 6)#define ACCDET_EINT1_CMPEN_STABLE_ADDR \#define ACCDET_EINT1_CMPEN_STABLE_SFT 7#define ACCDET_EINT1_CMPEN_STABLE_MASK 0x1#define ACCDET_EINT1_CMPEN_STABLE_MASK_SFT (0x1 << 7)#define ACCDET_EINT1_CMPMEN_STABLE_ADDR \#define ACCDET_EINT1_CMPMEN_STABLE_SFT 8#define ACCDET_EINT1_CMPMEN_STABLE_MASK 0x1#define ACCDET_EINT1_CMPMEN_STABLE_MASK_SFT (0x1 << 8)#define ACCDET_EINT1_CTURBO_STABLE_ADDR \#define ACCDET_EINT1_CTURBO_STABLE_SFT 9#define ACCDET_EINT1_CTURBO_STABLE_MASK 0x1#define ACCDET_EINT1_CTURBO_STABLE_MASK_SFT (0x1 << 9)#define ACCDET_EINT1_CEN_STABLE_ADDR \#define ACCDET_EINT1_CEN_STABLE_SFT 10#define ACCDET_EINT1_CEN_STABLE_MASK 0x1#define ACCDET_EINT1_CEN_STABLE_MASK_SFT (0x1 << 10)#define ACCDET_HWMODE_EN_ADDR \#define ACCDET_HWMODE_EN_SFT 0#define ACCDET_HWMODE_EN_MASK 0x1#define ACCDET_HWMODE_EN_MASK_SFT (0x1 << 0)#define ACCDET_HWMODE_SEL_ADDR \#define ACCDET_HWMODE_SEL_SFT 1#define ACCDET_HWMODE_SEL_MASK 0x3#define ACCDET_HWMODE_SEL_MASK_SFT (0x3 << 1)#define ACCDET_PLUG_OUT_DETECT_ADDR \#define ACCDET_PLUG_OUT_DETECT_SFT 3#define ACCDET_PLUG_OUT_DETECT_MASK 0x1#define ACCDET_PLUG_OUT_DETECT_MASK_SFT (0x1 << 3)#define ACCDET_EINT0_REVERSE_ADDR \#define ACCDET_EINT0_REVERSE_SFT 4#define ACCDET_EINT0_REVERSE_MASK 0x1#define ACCDET_EINT0_REVERSE_MASK_SFT (0x1 << 4)#define ACCDET_EINT1_REVERSE_ADDR \#define ACCDET_EINT1_REVERSE_SFT 5#define ACCDET_EINT1_REVERSE_MASK 0x1#define ACCDET_EINT1_REVERSE_MASK_SFT (0x1 << 5)#define ACCDET_EINT_HWMODE_EN_ADDR \#define ACCDET_EINT_HWMODE_EN_SFT 8#define ACCDET_EINT_HWMODE_EN_MASK 0x1#define ACCDET_EINT_HWMODE_EN_MASK_SFT (0x1 << 8)#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_ADDR \#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_SFT 9#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK 0x1#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK_SFT (0x1 << 9)#define ACCDET_EINT_M_PLUG_IN_EN_ADDR \#define ACCDET_EINT_M_PLUG_IN_EN_SFT 10#define ACCDET_EINT_M_PLUG_IN_EN_MASK 0x1#define ACCDET_EINT_M_PLUG_IN_EN_MASK_SFT (0x1 << 10)#define ACCDET_EINT_M_HWMODE_EN_ADDR \#define ACCDET_EINT_M_HWMODE_EN_SFT 11#define ACCDET_EINT_M_HWMODE_EN_MASK 0x1#define ACCDET_EINT_M_HWMODE_EN_MASK_SFT (0x1 << 11)#define ACCDET_TEST_CMPEN_ADDR \#define ACCDET_TEST_CMPEN_SFT 0#define ACCDET_TEST_CMPEN_MASK 0x1#define ACCDET_TEST_CMPEN_MASK_SFT (0x1 << 0)#define ACCDET_TEST_VTHEN_ADDR \#define ACCDET_TEST_VTHEN_SFT 1#define ACCDET_TEST_VTHEN_MASK 0x1#define ACCDET_TEST_VTHEN_MASK_SFT (0x1 << 1)#define ACCDET_TEST_MBIASEN_ADDR \#define ACCDET_TEST_MBIASEN_SFT 2#define ACCDET_TEST_MBIASEN_MASK 0x1#define ACCDET_TEST_MBIASEN_MASK_SFT (0x1 << 2)#define ACCDET_EINT_TEST_EN_ADDR \#define ACCDET_EINT_TEST_EN_SFT 3#define ACCDET_EINT_TEST_EN_MASK 0x1#define ACCDET_EINT_TEST_EN_MASK_SFT (0x1 << 3)#define ACCDET_EINT_TEST_INVEN_ADDR \#define ACCDET_EINT_TEST_INVEN_SFT 4#define ACCDET_EINT_TEST_INVEN_MASK 0x1#define ACCDET_EINT_TEST_INVEN_MASK_SFT (0x1 << 4)#define ACCDET_EINT_TEST_CMPEN_ADDR \#define ACCDET_EINT_TEST_CMPEN_SFT 5#define ACCDET_EINT_TEST_CMPEN_MASK 0x1#define ACCDET_EINT_TEST_CMPEN_MASK_SFT (0x1 << 5)#define ACCDET_EINT_TEST_CMPMEN_ADDR \#define ACCDET_EINT_TEST_CMPMEN_SFT 6#define ACCDET_EINT_TEST_CMPMEN_MASK 0x1#define ACCDET_EINT_TEST_CMPMEN_MASK_SFT (0x1 << 6)#define ACCDET_EINT_TEST_CTURBO_ADDR \#define ACCDET_EINT_TEST_CTURBO_SFT 7#define ACCDET_EINT_TEST_CTURBO_MASK 0x1#define ACCDET_EINT_TEST_CTURBO_MASK_SFT (0x1 << 7)#define ACCDET_EINT_TEST_CEN_ADDR \#define ACCDET_EINT_TEST_CEN_SFT 8#define ACCDET_EINT_TEST_CEN_MASK 0x1#define ACCDET_EINT_TEST_CEN_MASK_SFT (0x1 << 8)#define ACCDET_TEST_B_ADDR \#define ACCDET_TEST_B_SFT 9#define ACCDET_TEST_B_MASK 0x1#define ACCDET_TEST_B_MASK_SFT (0x1 << 9)#define ACCDET_TEST_A_ADDR \#define ACCDET_TEST_A_SFT 10#define ACCDET_TEST_A_MASK 0x1#define ACCDET_TEST_A_MASK_SFT (0x1 << 10)#define ACCDET_EINT_TEST_CMPOUT_ADDR \#define ACCDET_EINT_TEST_CMPOUT_SFT 11#define ACCDET_EINT_TEST_CMPOUT_MASK 0x1#define ACCDET_EINT_TEST_CMPOUT_MASK_SFT (0x1 << 11)#define ACCDET_EINT_TEST_CMPMOUT_ADDR \#define ACCDET_EINT_TEST_CMPMOUT_SFT 12#define ACCDET_EINT_TEST_CMPMOUT_MASK 0x1#define ACCDET_EINT_TEST_CMPMOUT_MASK_SFT (0x1 << 12)#define ACCDET_EINT_TEST_INVOUT_ADDR \#define ACCDET_EINT_TEST_INVOUT_SFT 13#define ACCDET_EINT_TEST_INVOUT_MASK 0x1#define ACCDET_EINT_TEST_INVOUT_MASK_SFT (0x1 << 13)#define ACCDET_CMPEN_SEL_ADDR \#define ACCDET_CMPEN_SEL_SFT 0#define ACCDET_CMPEN_SEL_MASK 0x1#define ACCDET_CMPEN_SEL_MASK_SFT (0x1 << 0)#define ACCDET_VTHEN_SEL_ADDR \#define ACCDET_VTHEN_SEL_SFT 1#define ACCDET_VTHEN_SEL_MASK 0x1#define ACCDET_VTHEN_SEL_MASK_SFT (0x1 << 1)#define ACCDET_MBIASEN_SEL_ADDR \#define ACCDET_MBIASEN_SEL_SFT 2#define ACCDET_MBIASEN_SEL_MASK 0x1#define ACCDET_MBIASEN_SEL_MASK_SFT (0x1 << 2)#define ACCDET_EINT_EN_SEL_ADDR \#define ACCDET_EINT_EN_SEL_SFT 3#define ACCDET_EINT_EN_SEL_MASK 0x1#define ACCDET_EINT_EN_SEL_MASK_SFT (0x1 << 3)#define ACCDET_EINT_INVEN_SEL_ADDR \#define ACCDET_EINT_INVEN_SEL_SFT 4#define ACCDET_EINT_INVEN_SEL_MASK 0x1#define ACCDET_EINT_INVEN_SEL_MASK_SFT (0x1 << 4)#define ACCDET_EINT_CMPEN_SEL_ADDR \#define ACCDET_EINT_CMPEN_SEL_SFT 5#define ACCDET_EINT_CMPEN_SEL_MASK 0x1#define ACCDET_EINT_CMPEN_SEL_MASK_SFT (0x1 << 5)#define ACCDET_EINT_CMPMEN_SEL_ADDR \#define ACCDET_EINT_CMPMEN_SEL_SFT 6#define ACCDET_EINT_CMPMEN_SEL_MASK 0x1#define ACCDET_EINT_CMPMEN_SEL_MASK_SFT (0x1 << 6)#define ACCDET_EINT_CTURBO_SEL_ADDR \#define ACCDET_EINT_CTURBO_SEL_SFT 7#define ACCDET_EINT_CTURBO_SEL_MASK 0x1#define ACCDET_EINT_CTURBO_SEL_MASK_SFT (0x1 << 7)#define ACCDET_B_SEL_ADDR \#define ACCDET_B_SEL_SFT 9#define ACCDET_B_SEL_MASK 0x1#define ACCDET_B_SEL_MASK_SFT (0x1 << 9)#define ACCDET_A_SEL_ADDR \#define ACCDET_A_SEL_SFT 10#define ACCDET_A_SEL_MASK 0x1#define ACCDET_A_SEL_MASK_SFT (0x1 << 10)#define ACCDET_EINT_CMPOUT_SEL_ADDR \#define ACCDET_EINT_CMPOUT_SEL_SFT 11#define ACCDET_EINT_CMPOUT_SEL_MASK 0x1#define ACCDET_EINT_CMPOUT_SEL_MASK_SFT (0x1 << 11)#define ACCDET_EINT_CMPMOUT_SEL_ADDR \#define ACCDET_EINT_CMPMOUT_SEL_SFT 12#define ACCDET_EINT_CMPMOUT_SEL_MASK 0x1#define ACCDET_EINT_CMPMOUT_SEL_MASK_SFT (0x1 << 12)#define ACCDET_EINT_INVOUT_SEL_ADDR \#define ACCDET_EINT_INVOUT_SEL_SFT 13#define ACCDET_EINT_INVOUT_SEL_MASK 0x1#define ACCDET_EINT_INVOUT_SEL_MASK_SFT (0x1 << 13)#define ACCDET_CMPEN_SW_ADDR \#define ACCDET_CMPEN_SW_SFT 0#define ACCDET_CMPEN_SW_MASK 0x1#define ACCDET_CMPEN_SW_MASK_SFT (0x1 << 0)#define ACCDET_VTHEN_SW_ADDR \#define ACCDET_VTHEN_SW_SFT 1#define ACCDET_VTHEN_SW_MASK 0x1#define ACCDET_VTHEN_SW_MASK_SFT (0x1 << 1)#define ACCDET_MBIASEN_SW_ADDR \#define ACCDET_MBIASEN_SW_SFT 2#define ACCDET_MBIASEN_SW_MASK 0x1#define ACCDET_MBIASEN_SW_MASK_SFT (0x1 << 2)#define ACCDET_EINT0_EN_SW_ADDR \#define ACCDET_EINT0_EN_SW_SFT 3#define ACCDET_EINT0_EN_SW_MASK 0x1#define ACCDET_EINT0_EN_SW_MASK_SFT (0x1 << 3)#define ACCDET_EINT0_INVEN_SW_ADDR \#define ACCDET_EINT0_INVEN_SW_SFT 4#define ACCDET_EINT0_INVEN_SW_MASK 0x1#define ACCDET_EINT0_INVEN_SW_MASK_SFT (0x1 << 4)#define ACCDET_EINT0_CMPEN_SW_ADDR \#define ACCDET_EINT0_CMPEN_SW_SFT 5#define ACCDET_EINT0_CMPEN_SW_MASK 0x1#define ACCDET_EINT0_CMPEN_SW_MASK_SFT (0x1 << 5)#define ACCDET_EINT0_CMPMEN_SW_ADDR \#define ACCDET_EINT0_CMPMEN_SW_SFT 6#define ACCDET_EINT0_CMPMEN_SW_MASK 0x1#define ACCDET_EINT0_CMPMEN_SW_MASK_SFT (0x1 << 6)#define ACCDET_EINT0_CTURBO_SW_ADDR \#define ACCDET_EINT0_CTURBO_SW_SFT 7#define ACCDET_EINT0_CTURBO_SW_MASK 0x1#define ACCDET_EINT0_CTURBO_SW_MASK_SFT (0x1 << 7)#define ACCDET_EINT1_EN_SW_ADDR \#define ACCDET_EINT1_EN_SW_SFT 8#define ACCDET_EINT1_EN_SW_MASK 0x1#define ACCDET_EINT1_EN_SW_MASK_SFT (0x1 << 8)#define ACCDET_EINT1_INVEN_SW_ADDR \#define ACCDET_EINT1_INVEN_SW_SFT 9#define ACCDET_EINT1_INVEN_SW_MASK 0x1#define ACCDET_EINT1_INVEN_SW_MASK_SFT (0x1 << 9)#define ACCDET_EINT1_CMPEN_SW_ADDR \#define ACCDET_EINT1_CMPEN_SW_SFT 10#define ACCDET_EINT1_CMPEN_SW_MASK 0x1#define ACCDET_EINT1_CMPEN_SW_MASK_SFT (0x1 << 10)#define ACCDET_EINT1_CMPMEN_SW_ADDR \#define ACCDET_EINT1_CMPMEN_SW_SFT 11#define ACCDET_EINT1_CMPMEN_SW_MASK 0x1#define ACCDET_EINT1_CMPMEN_SW_MASK_SFT (0x1 << 11)#define ACCDET_EINT1_CTURBO_SW_ADDR \#define ACCDET_EINT1_CTURBO_SW_SFT 12#define ACCDET_EINT1_CTURBO_SW_MASK 0x1#define ACCDET_EINT1_CTURBO_SW_MASK_SFT (0x1 << 12)#define ACCDET_B_SW_ADDR \#define ACCDET_B_SW_SFT 0#define ACCDET_B_SW_MASK 0x1#define ACCDET_B_SW_MASK_SFT (0x1 << 0)#define ACCDET_A_SW_ADDR \#define ACCDET_A_SW_SFT 1#define ACCDET_A_SW_MASK 0x1#define ACCDET_A_SW_MASK_SFT (0x1 << 1)#define ACCDET_EINT0_CMPOUT_SW_ADDR \#define ACCDET_EINT0_CMPOUT_SW_SFT 2#define ACCDET_EINT0_CMPOUT_SW_MASK 0x1#define ACCDET_EINT0_CMPOUT_SW_MASK_SFT (0x1 << 2)#define ACCDET_EINT0_CMPMOUT_SW_ADDR \#define ACCDET_EINT0_CMPMOUT_SW_SFT 3#define ACCDET_EINT0_CMPMOUT_SW_MASK 0x1#define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT (0x1 << 3)#define ACCDET_EINT0_INVOUT_SW_ADDR \#define ACCDET_EINT0_INVOUT_SW_SFT 4#define ACCDET_EINT0_INVOUT_SW_MASK 0x1#define ACCDET_EINT0_INVOUT_SW_MASK_SFT (0x1 << 4)#define ACCDET_EINT1_CMPOUT_SW_ADDR \#define ACCDET_EINT1_CMPOUT_SW_SFT 5#define ACCDET_EINT1_CMPOUT_SW_MASK 0x1#define ACCDET_EINT1_CMPOUT_SW_MASK_SFT (0x1 << 5)#define ACCDET_EINT1_CMPMOUT_SW_ADDR \#define ACCDET_EINT1_CMPMOUT_SW_SFT 6#define ACCDET_EINT1_CMPMOUT_SW_MASK 0x1#define ACCDET_EINT1_CMPMOUT_SW_MASK_SFT (0x1 << 6)#define ACCDET_EINT1_INVOUT_SW_ADDR \#define ACCDET_EINT1_INVOUT_SW_SFT 7#define ACCDET_EINT1_INVOUT_SW_MASK 0x1#define ACCDET_EINT1_INVOUT_SW_MASK_SFT (0x1 << 7)#define AD_AUDACCDETCMPOB_ADDR \#define AD_AUDACCDETCMPOB_SFT 0#define AD_AUDACCDETCMPOB_MASK 0x1#define AD_AUDACCDETCMPOB_MASK_SFT (0x1 << 0)#define AD_AUDACCDETCMPOA_ADDR \#define AD_AUDACCDETCMPOA_SFT 1#define AD_AUDACCDETCMPOA_MASK 0x1#define AD_AUDACCDETCMPOA_MASK_SFT (0x1 << 1)#define ACCDET_CUR_IN_ADDR \#define ACCDET_CUR_IN_SFT 2#define ACCDET_CUR_IN_MASK 0x3#define ACCDET_CUR_IN_MASK_SFT (0x3 << 2)#define ACCDET_SAM_IN_ADDR \#define ACCDET_SAM_IN_SFT 4#define ACCDET_SAM_IN_MASK 0x3
Messung V0.5 C=92 H=98 G=94
¤ Dauer der Verarbeitung: 0.25 Sekunden
(vorverarbeitet)
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