/* Should be able to read a single TPIDR... */
read_iov.iov_len = sizeof(uint64_t);
ret = ptrace(PTRACE_GETREGSET, child, NT_ARM_TLS, &read_iov);
ksft_test_result(ret == 0, "read_tpidr_one\n");
/* ...write a new value.. */
write_iov.iov_len = sizeof(uint64_t);
write_val[0] = read_val[0] + 1;
ret = ptrace(PTRACE_SETREGSET, child, NT_ARM_TLS, &write_iov);
ksft_test_result(ret == 0, "write_tpidr_one\n");
/* ...then read it back */
ret = ptrace(PTRACE_GETREGSET, child, NT_ARM_TLS, &read_iov);
ksft_test_result(ret == 0 && write_val[0] == read_val[0], "verify_tpidr_one\n");
/* If we have TPIDR2 we should be able to read it */
read_iov.iov_len = sizeof(read_val);
ret = ptrace(PTRACE_GETREGSET, child, NT_ARM_TLS, &read_iov); if (ret == 0) { /* If we have SME there should be two TPIDRs */ if (read_iov.iov_len >= sizeof(read_val))
test_tpidr2 = true;
if (test_tpidr2) { /* Try to write new values to all known TPIDRs... */
write_iov.iov_len = sizeof(write_val); for (i = 0; i < MAX_TPIDRS; i++)
write_val[i] = read_val[i] + 1;
ret = ptrace(PTRACE_SETREGSET, child, NT_ARM_TLS, &write_iov);
/* Should be able to read the values */
ret = ptrace(PTRACE_GETREGSET, child, type, &iov);
ksft_test_result(ret == 0, "read_%s\n", type_name);
if (ret == 0) { /* Low 8 bits is the number of slots, next 4 bits the arch */
slots = state.dbg_info & 0xff;
arch = (state.dbg_info >> 8) & 0xf;
ksft_print_msg("%s version %d with %d slots\n", type_name,
arch, slots);
/* Zero is not currently architecturally valid */
ksft_test_result(arch, "%s_arch_set\n", type_name);
} else {
ksft_test_result_skip("%s_arch_set\n", type_name);
}
}
staticint do_child(void)
{ if (ptrace(PTRACE_TRACEME, -1, NULL, NULL))
ksft_exit_fail_perror("PTRACE_TRACEME");
if (raise(SIGSTOP))
ksft_exit_fail_perror("raise(SIGSTOP)");
return EXIT_SUCCESS;
}
staticint do_parent(pid_t child)
{ int ret = EXIT_FAILURE;
pid_t pid; int status;
siginfo_t si;
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