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*/
// Declaration and definition of StubGenerator (no .hpp file). // For a more detailed description of the stub routine structure // see the comment in stubRoutines.hpp
// Platform dependent parameters for array copy stubs
// Note: we have noticed a huge change in behavior on a microbenchmark // from platform to platform depending on the configuration.
// Instead of adding a series of command line options (which // unfortunately have to be done in the shared file and cannot appear // only in the ARM port), the tested result are hard-coded here in a set // of options, selected by specifying 'ArmCopyPlatform'
// Currently, this 'platform' is hardcoded to a value that is a good // enough trade-off. However, one can easily modify this file to test // the hard-coded configurations or create new ones. If the gain is // significant, we could decide to either add command line options or // add code to automatically choose a configuration.
// see comments below for the various configurations created #define DEFAULT_ARRAYCOPY_CONFIG 0 #define TEGRA2_ARRAYCOPY_CONFIG 1 #define IMX515_ARRAYCOPY_CONFIG 2
// Hard coded choices (XXX: could be changed to a command line option) #define ArmCopyPlatform DEFAULT_ARRAYCOPY_CONFIG
#define ArmCopyCacheLineSize 32 // not worth optimizing to 64 according to measured gains
// configuration for each kind of loop typedefstruct { int pld_distance; // prefetch distance (0 => no prefetch, <0: prefetch_before); bool split_ldm; // if true, split each STM in STMs with fewer registers bool split_stm; // if true, split each LTM in LTMs with fewer registers
} arraycopy_loop_config;
// Configurations were chosen based on manual analysis of benchmark // results, minimizing overhead with respect to best results on the // different test cases.
// Prefetch before is always favored since it avoids dirtying the // cache uselessly for small copies. Code for prefetch after has // been kept in case the difference is significant for some // platforms but we might consider dropping it.
// distance, ldm, stm
{ // default: tradeoff tegra2/imx515/nv-tegra2, // Notes on benchmarking: // - not far from optimal configuration on nv-tegra2 // - within 5% of optimal configuration except for backward aligned on IMX // - up to 40% from optimal configuration for backward shifted and backward align for tegra2 // but still on par with the operating system copy
{-256, true, true }, // forward aligned
{-256, true, true }, // backward aligned
{-256, false, false }, // forward shifted
{-256, true, true } // backward shifted
},
{ // configuration tuned on tegra2-4. // Warning: should not be used on nv-tegra2 ! // Notes: // - prefetch after gives 40% gain on backward copies on tegra2-4, // resulting in better number than the operating system // copy. However, this can lead to a 300% loss on nv-tegra and has // more impact on the cache (fetches further than what is // copied). Use this configuration with care, in case it improves // reference benchmarks.
{-256, true, true }, // forward aligned
{96, false, false }, // backward aligned
{-256, false, false }, // forward shifted
{96, false, false } // backward shifted
},
{ // configuration tuned on imx515 // Notes: // - smaller prefetch distance is sufficient to get good result and might be more stable // - refined backward aligned options within 5% of optimal configuration except for // tests were the arrays fit in the cache
{-160, false, false }, // forward aligned
{-160, false, false }, // backward aligned
{-160, false, false }, // forward shifted
{-160, true, true } // backward shifted
}
};
// XXX: TODO // Would be better with respect to native tools if the following // setting of FP was changed to conform to the native ABI, with FP // pointing to the saved FP slot (and the corresponding modifications // for entry_frame_call_wrapper_offset and frame::real_fp).
__ mov(FP, SP);
// Check for special cases: divisor <= 0 or dividend < 0
__ cmp(divisor, 0);
__ orrs(quotient, dividend, divisor, ne);
__ b(negative_or_zero, le);
__ bind(positive_arguments); // Save return address on stack to free one extra register
__ push(LR); // Approximate the mamximum order of the quotient
__ clz(tmp, dividend);
__ clz(quotient, divisor);
__ subs(tmp, quotient, tmp);
__ mov(quotient, 0); // Jump to the appropriate place in the unrolled loop below
__ ldr(PC, Address(PC, tmp, lsl, 2), pl); // If divisor is greater than dividend, return immediately
__ pop(PC);
// Offset table
Label offset_table[32]; int i; for (i = 0; i <= 31; i++) {
__ emit_address(offset_table[i]);
}
// Unrolled loop of 32 division steps for (i = 31; i >= 0; i--) {
__ bind(offset_table[i]);
__ cmp(remainder, AsmOperand(divisor, lsl, i));
__ sub(remainder, remainder, AsmOperand(divisor, lsl, i), hs);
__ add(quotient, quotient, 1 << i, hs);
}
__ pop(PC);
__ bind(negative_or_zero); // Find the combination of argument signs and jump to corresponding handler
__ andr(quotient, dividend, 0x80000000, ne);
__ orr(quotient, quotient, AsmOperand(divisor, lsr, 31), ne);
__ add(PC, PC, AsmOperand(quotient, ror, 26), ne);
__ str(LR, Address(Rthread, JavaThread::saved_exception_pc_offset()));
// The leaf runtime function can destroy R0-R3 and R12 registers which are still alive
RegisterSet saved_registers = RegisterSet(R3) | RegisterSet(R12); #if R9_IS_SCRATCHED // Safer to save R9 here since callers may have been written // assuming R9 survives. This is suboptimal but may not be worth // revisiting for this slow case.
// As per atomic.hpp the Atomic read-modify-write operations must be logically implemented as: // <fence>; <op>; <membar StoreLoad|StoreStore> // But for load-linked/store-conditional based systems a fence here simply means // no load/store can be reordered with respect to the initial load-linked, so we have: // <membar storeload|loadload> ; load-linked; <op>; store-conditional; <membar storeload|storestore> // There are no memory actions in <op> so nothing further is needed. // // So we define the following for convenience: #define MEMBAR_ATOMIC_OP_PRE \
MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad|MacroAssembler::LoadLoad) #define MEMBAR_ATOMIC_OP_POST \
MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad|MacroAssembler::StoreStore)
// Note: JDK 9 only supports ARMv7+ so we always have ldrexd available even though the // code below allows for it to be otherwise. The else clause indicates an ARMv5 system // for which we do not support MP and so membars are not necessary. This ARMv5 code will // be removed in the future.
// Implementation of atomic_add(jint add_value, volatile jint* dest) // used by Atomic::add(volatile jint* dest, jint add_value) // // Arguments : // // add_value: R0 // dest: R1 // // Results: // // R0: the new stored in dest // // Overwrites: // // R1, R2, R3 //
address generate_atomic_add() {
address start;
// Stack is unaligned, maintain double word alignment by pushing // odd number of regs.
__ push(RegisterSet(temp_result) | RegisterSet(temp_lo, temp_hi));
__ ldr(addr, Address(SP, 12));
if (VM_Version::supports_ldrexd()) {
__ ldrexd(result_lo, Address(src));
__ clrex(); // FIXME: safe to remove?
} elseif (!os::is_MP()) { // Last-ditch attempt: we are allegedly running on uni-processor. // Load the thing non-atomically and hope for the best.
__ ldmia(src, RegisterSet(result_lo, result_hi));
} else {
__ stop("Atomic load(jlong) unsupported on this platform");
}
__ bx(LR);
StubCodeMark mark(this, "StubRoutines", "atomic_store_long");
start = __ pc(); Register newval_lo = R0; Register newval_hi = R1; Register dest = R2; Register scratch_lo = R2; Register scratch_hi = R3; /* After load from stack */ Register result = R3;
if (VM_Version::supports_ldrexd()) {
__ mov(Rtemp, dest); // get dest to Rtemp
Label retry;
__ bind(retry);
__ ldrexd(scratch_lo, Address(Rtemp));
__ strexd(result, R0, Address(Rtemp));
__ rsbs(result, result, 1);
__ b(retry, eq);
} elseif (!os::is_MP()) { // Last-ditch attempt: we are allegedly running on uni-processor. // Store the thing non-atomically and hope for the best.
__ stmia(dest, RegisterSet(newval_lo, newval_hi));
} else {
__ stop("Atomic store(jlong) unsupported on this platform");
}
__ bx(LR);
return start;
}
#ifdef COMPILER2 // Support for uint StubRoutine::Arm::partial_subtype_check( Klass sub, Klass super ); // Arguments : // // ret : R0, returned // icc/xcc: set as R0 (depending on wordSize) // sub : R1, argument, not changed // super: R2, argument, not changed // raddr: LR, blown by call
address generate_partial_subtype_check() {
__ align(CodeEntryAlignment);
StubCodeMark mark(this, "StubRoutines", "partial_subtype_check");
address start = __ pc();
// based on SPARC check_klass_subtype_[fast|slow]_path (without CompressedOops)
// R0 used as tmp_reg (in addition to return reg) Register sub_klass = R1; Register super_klass = R2; Register tmp_reg2 = R3; Register tmp_reg3 = R4; #define saved_set tmp_reg2, tmp_reg3
Label L_loop, L_fail;
int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
// fast check should be redundant
// slow check
{
__ raw_push(saved_set);
// a couple of useful fields in sub_klass: int ss_offset = in_bytes(Klass::secondary_supers_offset());
// Do a linear scan of the secondary super-klass chain. // This code is rarely used, so simplicity is a virtue here.
// Top of search loop
__ bind(L_loop); // Notes: // scan_temp starts at the array elements // count_temp is 1+size
__ subs(count_temp, count_temp, 1);
__ b(L_fail, eq); // not found in the array
// Load next super to check // In the array of super classes elements are pointer sized. int element_size = wordSize;
__ ldr(R0, Address(scan_temp, element_size, post_indexed));
// Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
__ subs(R0, R0, search_key); // set R0 to 0 on success (and flags to eq)
// A miss means we are NOT a subtype and need to keep looping
__ b(L_loop, ne);
// Falling out the bottom means we found a hit; we ARE a subtype
// Success. Cache the super we found and proceed in triumph.
__ str(super_klass, Address(sub_klass, sc_offset));
// Return success // R0 is already 0 and flags are already set to eq
__ raw_pop(saved_set);
__ ret();
// Incoming arguments: // // R0: error message (char* ) // R1: address of register save area // R2: oop to verify // // All registers are saved before calling this stub. However, condition flags should be saved here.
// make sure object is 'reasonable'
__ cbz(oop, exit); // if obj is NULL it is ok
// Check if the oop is in the right area of memory // Note: oop_mask and oop_bits must be updated if the code is saved/reused const address oop_mask = (address) Universe::verify_oop_mask(); const address oop_bits = (address) Universe::verify_oop_bits();
__ mov_address(tmp1, oop_mask);
__ andr(tmp2, oop, tmp1);
__ mov_address(tmp1, oop_bits);
__ cmp(tmp2, tmp1);
__ b(error, ne);
// make sure klass is 'reasonable'
__ load_klass(klass, oop); // get klass
__ cbz(klass, error); // if klass is NULL it is broken
// return if everything seems ok
__ bind(exit);
__ msr(Assembler::CPSR_f, flags);
__ ret();
// handle errors
__ bind(error);
__ mov(ret_addr, LR); // save return address
// R0: error message // R1: register save area
__ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug));
// probably we should choose between "prefetch-store before or after store", not "before or after load". void prefetch(Register from, Register to, int offset, int to_delta = 0) {
__ prefetch_read(Address(from, offset));
}
// Generate the inner loop for forward aligned array copy // // Arguments // from: src address, 64 bits aligned // to: dst address, wordSize aligned // count: number of elements (32-bit int) // bytes_per_count: number of bytes for each unit of 'count' // // Return the minimum initial value for count // // Notes: // - 'from' aligned on 64-bit (recommended for 32-bit ARM in case this speeds up LDMIA) // - 'to' aligned on wordSize // - 'count' must be greater or equal than the returned value // // Increases 'from' and 'to' by count*bytes_per_count. // // Scratches 'count', R3. // R4-R10 are preserved (saved/restored). // int generate_forward_aligned_copy_loop(Register from, Register to, Register count, int bytes_per_count, bool unsafe_copy = false) {
assert (from == R0 && to == R1 && count == R2, "adjust the implementation below");
constint bytes_per_loop = 8*wordSize; // 8 registers are read and written on every loop iteration
arraycopy_loop_config *config=&arraycopy_configurations[ArmCopyPlatform].forward_aligned; int pld_offset = config->pld_distance; constint count_per_loop = bytes_per_loop / bytes_per_count;
{ // UnsafeCopyMemory page error: continue after ucm
UnsafeCopyMemoryMark ucmm(this, unsafe_copy, true); // predecrease to exit when there is less than count_per_loop
__ sub_32(count, count, count_per_loop);
if (prefetch_before) { // If prefetch is done ahead, final PLDs that overflow the // copied area can be easily avoided. 'count' is predecreased // by the prefetch distance to optimize the inner loop and the // outer loop skips the PLD.
__ subs_32(count, count, (bytes_per_loop+pld_offset)/bytes_per_count);
// skip prefetch for small copies
__ b(L_skip_pld, lt);
}
int offset = ArmCopyCacheLineSize; while (offset <= pld_offset) {
prefetch(from, to, offset);
offset += ArmCopyCacheLineSize;
};
}
{ // 32-bit ARM note: we have tried implementing loop unrolling to skip one // PLD with 64 bytes cache line but the gain was not significant.
if (prefetch_before) {
prefetch(from, to, bytes_per_loop + pld_offset);
__ BIND(L_skip_pld);
}
if (split_read) { // Split the register set in two sets so that there is less // latency between LDM and STM (R3-R6 available while R7-R10 // still loading) and less register locking issue when iterating // on the first LDM.
__ ldmia(from, RegisterSet(R3, R6), writeback);
__ ldmia(from, RegisterSet(R7, R10), writeback);
} else {
__ ldmia(from, RegisterSet(R3, R10), writeback);
}
__ subs_32(count, count, count_per_loop);
if (prefetch_after) {
prefetch(from, to, pld_offset, bytes_per_loop);
}
if (prefetch_before) { // the inner loop may end earlier, allowing to skip PLD for the last iterations
__ cmn_32(count, (bytes_per_loop + pld_offset)/bytes_per_count);
__ b(L_skip_pld, ge);
}
}
BLOCK_COMMENT("Remaining bytes:"); // still 0..bytes_per_loop-1 aligned bytes to copy, count already decreased by (at least) bytes_per_loop bytes
// __ add(count, count, ...); // addition useless for the bit tests
assert (pld_offset % bytes_per_loop == 0, "decreasing count by pld_offset before loop must not change tested bits");
// Generate the inner loop for backward aligned array copy // // Arguments // end_from: src end address, 64 bits aligned // end_to: dst end address, wordSize aligned // count: number of elements (32-bit int) // bytes_per_count: number of bytes for each unit of 'count' // // Return the minimum initial value for count // // Notes: // - 'end_from' aligned on 64-bit (recommended for 32-bit ARM in case this speeds up LDMIA) // - 'end_to' aligned on wordSize // - 'count' must be greater or equal than the returned value // // Decreases 'end_from' and 'end_to' by count*bytes_per_count. // // Scratches 'count', R3. // ARM R4-R10 are preserved (saved/restored). // int generate_backward_aligned_copy_loop(Register end_from, Register end_to, Register count, int bytes_per_count, bool unsafe_copy = false) {
assert (end_from == R0 && end_to == R1 && count == R2, "adjust the implementation below");
constint bytes_per_loop = 8*wordSize; // 8 registers are read and written on every loop iteration constint count_per_loop = bytes_per_loop / bytes_per_count;
arraycopy_loop_config *config=&arraycopy_configurations[ArmCopyPlatform].backward_aligned; int pld_offset = config->pld_distance;
if (prefetch_before) {
__ cmn_32(count, (bytes_per_loop + pld_offset)/bytes_per_count);
__ b(L_skip_pld, ge);
}
}
BLOCK_COMMENT("Remaining bytes:"); // still 0..bytes_per_loop-1 aligned bytes to copy, count already decreased by (at least) bytes_per_loop bytes
// __ add(count, count, ...); // addition useless for the bit tests
assert (pld_offset % bytes_per_loop == 0, "decreasing count by pld_offset before loop must not change tested bits");
// Generate the inner loop for shifted forward array copy (unaligned copy). // It can be used when bytes_per_count < wordSize, i.e. byte/short copy // // Arguments // from: start src address, 64 bits aligned // to: start dst address, (now) wordSize aligned // count: number of elements (32-bit int) // bytes_per_count: number of bytes for each unit of 'count' // lsr_shift: shift applied to 'old' value to skipped already written bytes // lsl_shift: shift applied to 'new' value to set the high bytes of the next write // // Return the minimum initial value for count // // Notes: // - 'from' aligned on 64-bit (recommended for 32-bit ARM in case this speeds up LDMIA) // - 'to' aligned on wordSize // - 'count' must be greater or equal than the returned value // - 'lsr_shift' + 'lsl_shift' = BitsPerWord // - 'bytes_per_count' is 1 or 2 // // Increases 'to' by count*bytes_per_count. // // Scratches 'from' and 'count', R3-R10, R12 // // On entry: // - R12 is preloaded with the first 'BitsPerWord' bits read just before 'from' // - (R12 >> lsr_shift) is the part not yet written (just before 'to') // --> (*to) = (R12 >> lsr_shift) | (*from) << lsl_shift); ... // // This implementation may read more bytes than required. // Actually, it always reads exactly all data from the copied region with upper bound aligned up by wordSize, // so excessive read do not cross a word bound and is thus harmless. // int generate_forward_shifted_copy_loop(Register from, Register to, Register count, int bytes_per_count, int lsr_shift, int lsl_shift) {
assert (from == R0 && to == R1 && count == R2, "adjust the implementation below");
constint bytes_per_loop = 8*wordSize; // 8 registers are read and written on every loop iter constint count_per_loop = bytes_per_loop / bytes_per_count;
arraycopy_loop_config *config=&arraycopy_configurations[ArmCopyPlatform].forward_shifted; int pld_offset = config->pld_distance;
if (prefetch_before) { // do it early if there might be register locking issues
prefetch(from, to, bytes_per_loop + pld_offset);
__ BIND(L_skip_pld);
} else {
__ cmp_32(count, count_per_loop);
__ b(L_last_read, lt);
}
// read 32 bytes if (split_read) { // if write is not split, use less registers in first set to reduce locking
RegisterSet set1 = split_write ? RegisterSet(R4, R7) : RegisterSet(R4, R5);
RegisterSet set2 = (split_write ? RegisterSet(R8, R10) : RegisterSet(R6, R10)) | R12;
__ ldmia(from, set1, writeback);
__ mov(R3, AsmOperand(R12, lsr, lsr_shift)); // part of R12 not yet written
__ ldmia(from, set2, writeback);
__ subs(count, count, count_per_loop); // XXX: should it be before the 2nd LDM ? (latency vs locking)
} else {
__ mov(R3, AsmOperand(R12, lsr, lsr_shift)); // part of R12 not yet written
__ ldmia(from, RegisterSet(R4, R10) | R12, writeback); // Note: small latency on R4
__ subs(count, count, count_per_loop);
}
if (prefetch_after) { // do it after the 1st ldm/ldp anyway (no locking issues with early STM/STP)
prefetch(from, to, pld_offset, bytes_per_loop);
}
// prepare (shift) the values in R3..R10
__ orr(R3, R3, AsmOperand(R4, lsl, lsl_shift)); // merged below low bytes of next val
__ logical_shift_right(R4, R4, lsr_shift); // unused part of next val
__ orr(R4, R4, AsmOperand(R5, lsl, lsl_shift)); // ...
__ logical_shift_right(R5, R5, lsr_shift);
__ orr(R5, R5, AsmOperand(R6, lsl, lsl_shift));
__ logical_shift_right(R6, R6, lsr_shift);
__ orr(R6, R6, AsmOperand(R7, lsl, lsl_shift)); if (split_write) { // write the first half as soon as possible to reduce stm locking
__ stmia(to, RegisterSet(R3, R6), writeback, prefetch_before ? gt : ge);
}
__ logical_shift_right(R7, R7, lsr_shift);
__ orr(R7, R7, AsmOperand(R8, lsl, lsl_shift));
__ logical_shift_right(R8, R8, lsr_shift);
__ orr(R8, R8, AsmOperand(R9, lsl, lsl_shift));
__ logical_shift_right(R9, R9, lsr_shift);
__ orr(R9, R9, AsmOperand(R10, lsl, lsl_shift));
__ logical_shift_right(R10, R10, lsr_shift);
__ orr(R10, R10, AsmOperand(R12, lsl, lsl_shift));
if (split_write) {
__ stmia(to, RegisterSet(R7, R10), writeback, prefetch_before ? gt : ge);
} else {
__ stmia(to, RegisterSet(R3, R10), writeback, prefetch_before ? gt : ge);
}
__ b(L_shifted_loop, gt); // no need to loop if 0 (when count need not be precise modulo bytes_per_loop)
if (prefetch_before) { // the first loop may end earlier, allowing to skip pld at the end
__ cmn_32(count, (bytes_per_loop + pld_offset)/bytes_per_count);
__ stmia(to, RegisterSet(R3, R10), writeback); // stmia was skipped
__ b(L_skip_pld, ge);
__ adds_32(count, count, ((bytes_per_loop + pld_offset) / bytes_per_count) + count_per_loop);
}
// Note: R3 might contain enough bytes ready to write (3 needed at most), // thus load on lsl_shift==24 is not needed (in fact forces reading // beyond source buffer end boundary) if (lsl_shift == 8) {
__ ldr(R4, Address(from, 4, post_indexed), ge);
__ orr(R3, R3, AsmOperand(R4, lsl, lsl_shift), ge);
} elseif (lsl_shift == 16) {
__ ldr(R4, Address(from, 4, post_indexed), gt);
__ orr(R3, R3, AsmOperand(R4, lsl, lsl_shift), gt);
}
__ strh(R3, Address(to, 2, post_indexed), ge); // two last bytes
__ mov(R3, AsmOperand(R3, lsr, 16), gt);
__ tst(count, 1);
__ strb(R3, Address(to, 1, post_indexed), ne); // one last byte break;
}
__ BIND(L_done); return 0; // no minimum
}
// Generate the inner loop for shifted backward array copy (unaligned copy). // It can be used when bytes_per_count < wordSize, i.e. byte/short copy // // Arguments // end_from: end src address, 64 bits aligned // end_to: end dst address, (now) wordSize aligned // count: number of elements (32-bit int) // bytes_per_count: number of bytes for each unit of 'count' // lsl_shift: shift applied to 'old' value to skipped already written bytes // lsr_shift: shift applied to 'new' value to set the low bytes of the next write // // Return the minimum initial value for count // // Notes: // - 'end_from' aligned on 64-bit (recommended for 32-bit ARM in case this speeds up LDMIA) // - 'end_to' aligned on wordSize // - 'count' must be greater or equal than the returned value // - 'lsr_shift' + 'lsl_shift' = 'BitsPerWord' // - 'bytes_per_count' is 1 or 2 on 32-bit ARM // // Decreases 'end_to' by count*bytes_per_count. // // Scratches 'end_from', 'count', R3-R10, R12 // // On entry: // - R3 is preloaded with the first 'BitsPerWord' bits read just after 'from' // - (R3 << lsl_shift) is the part not yet written // --> (*--to) = (R3 << lsl_shift) | (*--from) >> lsr_shift); ... // // This implementation may read more bytes than required. // Actually, it always reads exactly all data from the copied region with beginning aligned down by wordSize, // so excessive read do not cross a word bound and is thus harmless. // int generate_backward_shifted_copy_loop(Register end_from, Register end_to, Register count, int bytes_per_count, int lsr_shift, int lsl_shift) {
assert (end_from == R0 && end_to == R1 && count == R2, "adjust the implementation below");
constint bytes_per_loop = 8*wordSize; // 8 registers are read and written on every loop iter constint count_per_loop = bytes_per_loop / bytes_per_count;
arraycopy_loop_config *config=&arraycopy_configurations[ArmCopyPlatform].backward_shifted; int pld_offset = config->pld_distance;
if (prefetch_before) {
__ cmp_32(count, count_per_loop);
__ b(L_last_read, lt);
// skip prefetch for small copies // warning: count is predecreased by the prefetch distance to optimize the inner loop
__ subs_32(count, count, ((bytes_per_loop + pld_offset)/bytes_per_count) + count_per_loop);
__ b(L_skip_pld, lt);
}
int offset = ArmCopyCacheLineSize; while (offset <= pld_offset) {
prefetch(end_from, end_to, -(wordSize + offset));
offset += ArmCopyCacheLineSize;
};
}
if (prefetch_before) { // do the 1st ldm/ldp first anyway (no locking issues with early STM/STP)
prefetch(end_from, end_to, -(wordSize + bytes_per_loop + pld_offset));
__ BIND(L_skip_pld);
} else {
__ cmp_32(count, count_per_loop);
__ b(L_last_read, lt);
}
if (split_read) {
__ ldmdb(end_from, RegisterSet(R7, R10), writeback);
__ mov(R12, AsmOperand(R3, lsl, lsl_shift)); // part of R3 not yet written
__ ldmdb(end_from, RegisterSet(R3, R6), writeback);
} else {
__ mov(R12, AsmOperand(R3, lsl, lsl_shift)); // part of R3 not yet written
__ ldmdb(end_from, RegisterSet(R3, R10), writeback);
}
__ subs_32(count, count, count_per_loop);
if (prefetch_after) { // do prefetch during ldm/ldp latency
prefetch(end_from, end_to, -(wordSize + pld_offset), -bytes_per_loop);
}
__ b(L_shifted_loop, gt); // no need to loop if 0 (when count need not be precise modulo bytes_per_loop)
if (prefetch_before) { // the first loop may end earlier, allowing to skip pld at the end
__ cmn_32(count, ((bytes_per_loop + pld_offset)/bytes_per_count));
__ stmdb(end_to, RegisterSet(R4, R10) | R12, writeback); // stmdb was skipped
__ b(L_skip_pld, ge);
__ adds_32(count, count, ((bytes_per_loop + pld_offset) / bytes_per_count) + count_per_loop);
}
// Copies data from 'from' to 'to' in specified direction to align 'from' by 64 bits. // (on 32-bit ARM 64-bit alignment is better for LDM). // // Arguments: // from: beginning (if forward) or upper bound (if !forward) of the region to be read // to: beginning (if forward) or upper bound (if !forward) of the region to be written // count: 32-bit int, maximum number of elements which can be copied // bytes_per_count: size of an element // forward: specifies copy direction // // Notes: // 'from' and 'to' must be aligned by 'bytes_per_count' // 'count' must not be less than the returned value // shifts 'from' and 'to' by the number of copied bytes in corresponding direction // decreases 'count' by the number of elements copied // // Returns maximum number of bytes which may be copied. int align_src(Register from, Register to, Register count, Register tmp, int bytes_per_count, bool forward) {
assert_different_registers(from, to, count, tmp); if (bytes_per_count < 8) {
Label L_align_src;
__ BIND(L_align_src);
__ tst(from, 7); // ne => not aligned: copy one element and (if bytes_per_count < 4) loop
__ sub(count, count, 1, ne);
load_one(tmp, from, bytes_per_count, forward, ne);
store_one(tmp, to, bytes_per_count, forward, ne); if (bytes_per_count < 4) {
__ b(L_align_src, ne); // if bytes_per_count == 4, then 0 or 1 loop iterations are enough
}
} return 7/bytes_per_count;
}
// Copies 'count' of 'bytes_per_count'-sized elements in the specified direction. // // Arguments: // from: beginning (if forward) or upper bound (if !forward) of the region to be read // to: beginning (if forward) or upper bound (if !forward) of the region to be written // count: 32-bit int, number of elements to be copied // entry: copy loop entry point // bytes_per_count: size of an element // forward: specifies copy direction // // Notes: // shifts 'from' and 'to' void copy_small_array(Register from, Register to, Register count, Register tmp, Register tmp2, int bytes_per_count, bool forward, Label & entry, bool unsafe_copy = false) {
assert_different_registers(from, to, count, tmp);
// Aligns 'to' by reading one word from 'from' and writing its part to 'to'. // // Arguments: // to: beginning (if forward) or upper bound (if !forward) of the region to be written // count: 32-bit int, number of elements allowed to be copied // to_remainder: remainder of dividing 'to' by wordSize // bytes_per_count: size of an element // forward: specifies copy direction // Rval: contains an already read but not yet written word; // its' LSBs (if forward) or MSBs (if !forward) are to be written to align 'to'. // // Notes: // 'count' must not be less then the returned value // 'to' must be aligned by bytes_per_count but must not be aligned by wordSize // shifts 'to' by the number of written bytes (so that it becomes the bound of memory to be written) // decreases 'count' by the number of elements written // Rval's MSBs or LSBs remain to be written further by generate_{forward,backward}_shifted_copy_loop int align_dst(Register to, Register count, Register Rval, Register tmp, int to_remainder, int bytes_per_count, bool forward) {
assert_different_registers(to, count, tmp, Rval);
assert (0 < to_remainder && to_remainder < wordSize, "to_remainder is not valid");
assert (to_remainder % bytes_per_count == 0, "to must be aligned by bytes_per_count");
int bytes_to_write = forward ? (wordSize - to_remainder) : to_remainder;
int offset = 0;
for (int l = 0; l < LogBytesPerWord; ++l) { int s = (1 << l); if (bytes_to_write & s) { int new_offset = offset + s*BitsPerByte; if (forward) { if (offset == 0) {
store_one(Rval, to, s, forward);
} else {
__ logical_shift_right(tmp, Rval, offset);
store_one(tmp, to, s, forward);
}
} else {
--> --------------------
--> maximum size reached
--> --------------------
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