/* * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, 2019 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. *
*/
// Returns true if reg could be smashed by a callee. bool FrameMap::is_caller_save_register (LIR_Opr reg) { if (reg->is_single_fpu() || reg->is_double_fpu()) { returntrue; } if (reg->is_double_cpu()) { return is_caller_save_register(reg->as_register_lo()) ||
is_caller_save_register(reg->as_register_hi());
} return is_caller_save_register(reg->as_register());
}
bool FrameMap::is_caller_save_register (Register r) { // not visible to allocator: R0: scratch, R1: SP // r->encoding() < 2 + nof_caller_save_cpu_regs(); returntrue; // Currently all regs are caller save.
}
// Put generally available registers at the beginning (allocated, saved for GC). for (int j = 0; j < nof_cpu_regs; ++j) { Register rj = as_Register(j); if (reg_needs_save(rj)) {
map_register(i++, rj);
}
}
assert(i == nof_cpu_regs_reg_alloc, "number of allocated registers");
// The following registers are not normally available. for (int j = 0; j < nof_cpu_regs; ++j) { Register rj = as_Register(j); if (!reg_needs_save(rj)) {
map_register(i++, rj);
}
}
assert(i == nof_cpu_regs, "number of CPU registers");
for (i = 0; i < nof_fpu_regs; i++) {
_fpu_regs[i] = as_FloatRegister(i);
}
// All the allocated cpu regs are caller saved. for (int i = 0; i < max_nof_caller_save_cpu_regs; i++) {
_caller_save_cpu_regs[i] = LIR_OprFact::single_cpu(i);
}
// All the fpu regs are caller saved. for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
}
}
// JSR 292 // On PPC64, there is no need to save the SP, because neither // method handle intrinsics, nor compiled lambda forms modify it.
LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { return LIR_OprFact::illegalOpr;
}
bool FrameMap::validate_frame() { int max_offset = in_bytes(framesize_in_bytes()); int java_index = 0; for (int i = 0; i < _incoming_arguments->length(); i++) {
LIR_Opr opr = _incoming_arguments->at(i); if (opr->is_stack()) {
max_offset = MAX2(_argument_locations->at(java_index), max_offset);
}
java_index += type2size[opr->type()];
} return Assembler::is_simm16(max_offset);
}
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