/* * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. *
*/
char LIR_Opr::type_char(BasicType t) { switch (t) { case T_ARRAY:
t = T_OBJECT; case T_BOOLEAN: case T_CHAR: case T_FLOAT: case T_DOUBLE: case T_BYTE: case T_SHORT: case T_INT: case T_LONG: case T_OBJECT: case T_ADDRESS: case T_VOID: return ::type2char(t); case T_METADATA: return'M'; case T_ILLEGAL: return'?';
#ifdef ASSERT if (!is_pointer() && !is_illegal()) {
OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 switch (as_BasicType(type_field())) { case T_LONG:
assert((kindfield == cpu_register || kindfield == stack_value) &&
size_field() == double_size, "must match"); break; case T_FLOAT: // FP return values can be also in CPU registers on ARM (softfp ABI)
assert((kindfield == fpu_register || kindfield == stack_value
ARM_ONLY(|| kindfield == cpu_register) ) &&
size_field() == single_size, "must match"); break; case T_DOUBLE: // FP return values can be also in CPU registers on ARM (softfp ABI)
assert((kindfield == fpu_register || kindfield == stack_value
ARM_ONLY(|| kindfield == cpu_register) ) &&
size_field() == double_size, "must match"); break; case T_BOOLEAN: case T_CHAR: case T_BYTE: case T_SHORT: case T_INT: case T_ADDRESS: case T_OBJECT: case T_METADATA: case T_ARRAY:
assert((kindfield == cpu_register || kindfield == stack_value) &&
size_field() == single_size, "must match"); break;
case T_ILLEGAL: // XXX TKR also means unknown right now // assert(is_illegal(), "must match"); break;
default:
assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), "can't produce oops from arith");
}
if (TwoOperandLIRForm) {
#ifdef ASSERT bool threeOperandForm = false; #ifdef S390 // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
threeOperandForm =
code() == lir_shl ||
((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT)); #endif #endif
switch (code()) { case lir_add: case lir_sub: case lir_mul: case lir_div: case lir_rem: case lir_logic_and: case lir_logic_or: case lir_logic_xor: case lir_shl: case lir_shr:
assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); break;
// special handling for lir_ushr because of write barriers case lir_ushr:
assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); break;
// complete rework of LIR instruction visitor. // The virtual call for each instruction type is replaced by a big // switch that adds the operands for each instruction
void LIR_OpVisitState::visit(LIR_Op* op) { // copy information from the LIR_Op
reset();
set_op(op);
switch (op->code()) {
// LIR_Op0 case lir_fpop_raw: // result and info always invalid case lir_breakpoint: // result and info always invalid case lir_membar: // result and info always invalid case lir_membar_acquire: // result and info always invalid case lir_membar_release: // result and info always invalid case lir_membar_loadload: // result and info always invalid case lir_membar_storestore: // result and info always invalid case lir_membar_loadstore: // result and info always invalid case lir_membar_storeload: // result and info always invalid case lir_on_spin_wait:
{
assert(op->as_Op0() != NULL, "must be");
assert(op->_info == NULL, "info not used by this instruction");
assert(op->_result->is_illegal(), "not used"); break;
}
case lir_nop: // may have info, result always invalid case lir_std_entry: // may have result, info always invalid case lir_osr_entry: // may have result, info always invalid case lir_get_thread: // may have result, info always invalid
{
assert(op->as_Op0() != NULL, "must be"); if (op->_info != NULL) do_info(op->_info); if (op->_result->is_valid()) do_output(op->_result); break;
}
// LIR_OpLabel case lir_label: // result and info always invalid
{
assert(op->as_OpLabel() != NULL, "must be");
assert(op->_info == NULL, "info not used by this instruction");
assert(op->_result->is_illegal(), "not used"); break;
}
// LIR_Op1 case lir_fxch: // input always valid, result and info always invalid case lir_fld: // input always valid, result and info always invalid case lir_push: // input always valid, result and info always invalid case lir_pop: // input always valid, result and info always invalid case lir_leal: // input and result always valid, info always invalid case lir_monaddr: // input and result always valid, info always invalid case lir_null_check: // input and info always valid, result always invalid case lir_move: // input and result always valid, may have info
{
assert(op->as_Op1() != NULL, "must be");
LIR_Op1* op1 = (LIR_Op1*)op;
if (op1->_info) do_info(op1->_info); if (op1->_opr->is_valid()) do_input(op1->_opr); if (op1->_result->is_valid()) do_output(op1->_result);
if (op_ret->_info) do_info(op_ret->_info); if (op_ret->_opr->is_valid()) do_input(op_ret->_opr); if (op_ret->_result->is_valid()) do_output(op_ret->_result); if (op_ret->stub() != NULL) do_stub(op_ret->stub());
assert(op1->_info != NULL, ""); do_info(op1->_info); if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
assert(op1->_result->is_illegal(), "safepoint does not produce value");
break;
}
// LIR_OpConvert; case lir_convert: // input and result always valid, info always invalid
{
assert(op->as_OpConvert() != NULL, "must be");
LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
assert(opConvert->_info == NULL, "must be"); if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); if (opConvert->_result->is_valid()) do_output(opConvert->_result);
do_stub(opConvert->_stub);
break;
}
// LIR_OpBranch; case lir_branch: // may have info, input and result register always invalid case lir_cond_float_branch: // may have info, input and result register always invalid
{
assert(op->as_OpBranch() != NULL, "must be");
LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
if (opAllocObj->_info) do_info(opAllocObj->_info); if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
do_temp(opAllocObj->_opr);
} if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); if (opAllocObj->_stub != nullptr) do_stub(opAllocObj->_stub); break;
}
assert(op->_info == NULL, "info not used by this instruction");
assert(opRoundFP->_tmp->is_illegal(), "not used");
do_input(opRoundFP->_opr);
do_output(opRoundFP->_result);
break;
}
// LIR_Op2 case lir_cmp: case lir_cmp_l2i: case lir_ucmp_fd2i: case lir_cmp_fd2i: case lir_add: case lir_sub: case lir_rem: case lir_sqrt: case lir_abs: case lir_neg: case lir_logic_and: case lir_logic_or: case lir_logic_xor: case lir_shl: case lir_shr: case lir_ushr: case lir_xadd: case lir_xchg: case lir_assert:
{
assert(op->as_Op2() != NULL, "must be");
LIR_Op2* op2 = (LIR_Op2*)op;
assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
if (op2->_info) do_info(op2->_info); if (op2->_opr1->is_valid()) do_input(op2->_opr1); if (op2->_opr2->is_valid()) do_input(op2->_opr2); if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); if (op2->_result->is_valid()) do_output(op2->_result); if (op->code() == lir_xchg || op->code() == lir_xadd) { // on ARM and PPC, return value is loaded first so could // destroy inputs. On other platforms that implement those // (x86, sparc), the extra constrainsts are harmless. if (op2->_opr1->is_valid()) do_temp(op2->_opr1); if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
}
break;
}
// special handling for cmove: right input operand must not be equal // to the result operand, otherwise the backend fails case lir_cmove:
{
assert(op->as_Op4() != NULL, "must be");
LIR_Op4* op4 = (LIR_Op4*)op;
do_input(op4->_opr1);
do_input(op4->_opr2); if (op4->_opr3->is_valid()) do_input(op4->_opr3); if (op4->_opr4->is_valid()) do_input(op4->_opr4);
do_temp(op4->_opr2);
do_output(op4->_result);
break;
}
// vspecial handling for strict operations: register input operands // as temp to guarantee that they do not overlap with other // registers case lir_mul: case lir_div:
{
assert(op->as_Op2() != NULL, "must be");
LIR_Op2* op2 = (LIR_Op2*)op;
assert(op1->_info == NULL, "no info");
assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
assert(op1->_result->is_illegal(), "no result");
break;
}
// LIR_Op3 case lir_idiv: case lir_irem: {
assert(op->as_Op3() != NULL, "must be");
LIR_Op3* op3= (LIR_Op3*)op;
if (op3->_info) do_info(op3->_info); if (op3->_opr1->is_valid()) do_input(op3->_opr1);
// second operand is input and temp, so ensure that second operand // and third operand get not the same register if (op3->_opr2->is_valid()) do_input(op3->_opr2); if (op3->_opr2->is_valid()) do_temp(op3->_opr2); if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
if (op3->_result->is_valid()) do_output(op3->_result);
break;
}
case lir_fmad: case lir_fmaf: {
assert(op->as_Op3() != NULL, "must be");
LIR_Op3* op3= (LIR_Op3*)op;
assert(op3->_info == NULL, "no info");
do_input(op3->_opr1);
do_input(op3->_opr2);
do_input(op3->_opr3);
do_output(op3->_result); break;
}
// LIR_OpJavaCall case lir_static_call: case lir_optvirtual_call: case lir_icvirtual_call: case lir_dynamic_call: {
LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
assert(opJavaCall != NULL, "must be");
if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
// only visit register parameters int n = opJavaCall->_arguments->length(); for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { if (!opJavaCall->_arguments->at(i)->is_pointer()) {
do_input(*opJavaCall->_arguments->adr_at(i));
}
}
if (opJavaCall->_info) do_info(opJavaCall->_info); if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
opJavaCall->is_method_handle_invoke()) {
opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
}
do_call(); if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
// only visit register parameters int n = opRTCall->_arguments->length(); for (int i = 0; i < n; i++) { if (!opRTCall->_arguments->at(i)->is_pointer()) {
do_input(*opRTCall->_arguments->adr_at(i));
}
} if (opRTCall->_info) do_info(opRTCall->_info); if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
do_call(); if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
break;
}
// LIR_OpLock case lir_lock: case lir_unlock: {
assert(op->as_OpLock() != NULL, "must be");
LIR_OpLock* opLock = (LIR_OpLock*)op;
if (opLock->_info) do_info(opLock->_info);
// TODO: check if these operands really have to be temp // (or if input is sufficient). This may have influence on the oop map!
assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
assert(opLock->_result->is_illegal(), "unused");
// LIR_OpTypeCheck case lir_instanceof: case lir_checkcast: case lir_store_check: {
assert(op->as_OpTypeCheck() != NULL, "must be");
LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
do_temp(opTypeCheck->_object);
} if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); if (opTypeCheck->_stub != nullptr) do_stub(opTypeCheck->_stub); break;
}
// LIR_OpCompareAndSwap case lir_cas_long: case lir_cas_obj: case lir_cas_int: {
assert(op->as_OpCompareAndSwap() != NULL, "must be");
LIR_OpCompareAndSwap* opCmpAndSwap = (LIR_OpCompareAndSwap*)op;
if (opCmpAndSwap->_info) do_info(opCmpAndSwap->_info);
assert(opCmpAndSwap->_addr->is_valid(), "used"); do_input(opCmpAndSwap->_addr);
do_temp(opCmpAndSwap->_addr);
assert(opCmpAndSwap->_cmp_value->is_valid(), "used"); do_input(opCmpAndSwap->_cmp_value);
do_temp(opCmpAndSwap->_cmp_value);
assert(opCmpAndSwap->_new_value->is_valid(), "used"); do_input(opCmpAndSwap->_new_value);
do_temp(opCmpAndSwap->_new_value); if (opCmpAndSwap->_tmp1->is_valid()) do_temp(opCmpAndSwap->_tmp1); if (opCmpAndSwap->_tmp2->is_valid()) do_temp(opCmpAndSwap->_tmp2); if (opCmpAndSwap->_result->is_valid()) do_output(opCmpAndSwap->_result);
if (opAllocArray->_info) do_info(opAllocArray->_info); if (opAllocArray->_klass->is_valid()) { do_input(opAllocArray->_klass);
do_temp(opAllocArray->_klass);
} if (opAllocArray->_len->is_valid()) { do_input(opAllocArray->_len);
do_temp(opAllocArray->_len);
} if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); if (opAllocArray->_stub != nullptr) do_stub(opAllocArray->_stub); break;
}
XHandlers* LIR_OpVisitState::all_xhandler() {
XHandlers* result = NULL;
int i; for (i = 0; i < info_count(); i++) { if (info_at(i)->exception_handlers() != NULL) {
result = info_at(i)->exception_handlers(); break;
}
}
#ifdef ASSERT for (i = 0; i < info_count(); i++) {
assert(info_at(i)->exception_handlers() == NULL ||
info_at(i)->exception_handlers() == result, "only one xhandler list allowed per LIR-operation");
} #endif
if (buffer->number_of_ops() > 0) { // increase size of instructions list
_operations.at_grow(n + buffer->number_of_ops() - 1, NULL); // insert ops from buffer into instructions list int op_index = buffer->number_of_ops() - 1; int ip_index = buffer->number_of_insertion_points() - 1; int from_index = n - 1; int to_index = _operations.length() - 1; for (; ip_index >= 0; ip_index --) { int index = buffer->index_at(ip_index); // make room after insertion point while (index < from_index) {
_operations.at_put(to_index --, _operations.at(from_index --));
} // insert ops from buffer for (int i = buffer->count_at(ip_index); i > 0; i --) {
_operations.at_put(to_index --, buffer->op_at(op_index --));
}
}
}
void check_LIR() { // cannot do the proper checking as PRODUCT and other modes return different results // guarantee(sizeof(LIR_Opr) == wordSize, "may not have a v-table");
}
// LIR_Address void LIR_Const::print_value_on(outputStream* out) const { switch (type()) { case T_ADDRESS:out->print("address:%d",as_jint()); break; case T_INT: out->print("int:%d", as_jint()); break; case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; case T_FLOAT: out->print("flt:%f", as_jfloat()); break; case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; default: out->print("%3d:" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
}
}
// LIR_Address void LIR_Address::print_value_on(outputStream* out) const {
out->print("Base:"); _base->print(out); if (!_index->is_illegal()) {
out->print(" Index:"); _index->print(out); switch (scale()) { case times_1: break; case times_2: out->print(" * 2"); break; case times_4: out->print(" * 4"); break; case times_8: out->print(" * 8"); break;
}
}
out->print(" Disp: " INTX_FORMAT, _disp);
}
// debug output of block header without InstructionPrinter // (because phi functions are not necessary for LIR) staticvoid print_block(BlockBegin* x) { // print block id
BlockEnd* end = x->end();
tty->print("B%d ", x->block_id());
// print flags if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
// print predecessors and successors if (x->number_of_preds() > 0) {
tty->print("preds: "); for (int i = 0; i < x->number_of_preds(); i ++) {
tty->print("B%d ", x->pred_at(i)->block_id());
}
}
if (end != NULL && x->number_of_sux() > 0) {
tty->print("sux: "); for (int i = 0; i < x->number_of_sux(); i ++) {
tty->print("B%d ", x->sux_at(i)->block_id());
}
}
// print exception handlers if (x->number_of_exception_handlers() > 0) {
tty->print("xhandler: "); for (int i = 0; i < x->number_of_exception_handlers(); i++) {
tty->print("B%d ", x->exception_handler_at(i)->block_id());
}
}
tty->cr();
}
void print_LIR(BlockList* blocks) {
tty->print_cr("LIR:"); int i; for (i = 0; i < blocks->length(); i++) {
BlockBegin* bb = blocks->at(i);
print_block(bb);
tty->print("__id_Instruction___________________________________________"); tty->cr();
bb->lir()->print_instructions();
}
}
void LIR_List::print_instructions() { for (int i = 0; i < _operations.length(); i++) {
_operations.at(i)->print(); tty->cr();
}
tty->cr();
}
constchar * LIR_Op::name() const { constchar* s = NULL; switch(code()) { // LIR_Op0 case lir_membar: s = "membar"; break; case lir_membar_acquire: s = "membar_acquire"; break; case lir_membar_release: s = "membar_release"; break; case lir_membar_loadload: s = "membar_loadload"; break; case lir_membar_storestore: s = "membar_storestore"; break; case lir_membar_loadstore: s = "membar_loadstore"; break; case lir_membar_storeload: s = "membar_storeload"; break; case lir_label: s = "label"; break; case lir_nop: s = "nop"; break; case lir_on_spin_wait: s = "on_spin_wait"; break; case lir_std_entry: s = "std_entry"; break; case lir_osr_entry: s = "osr_entry"; break; case lir_fpop_raw: s = "fpop_raw"; break; case lir_breakpoint: s = "breakpoint"; break; case lir_get_thread: s = "get_thread"; break; // LIR_Op1 case lir_fxch: s = "fxch"; break; case lir_fld: s = "fld"; break; case lir_push: s = "push"; break; case lir_pop: s = "pop"; break; case lir_null_check: s = "null_check"; break; case lir_return: s = "return"; break; case lir_safepoint: s = "safepoint"; break; case lir_leal: s = "leal"; break; case lir_branch: s = "branch"; break; case lir_cond_float_branch: s = "flt_cond_br"; break; case lir_move: s = "move"; break; case lir_roundfp: s = "roundfp"; break; case lir_rtcall: s = "rtcall"; break; case lir_throw: s = "throw"; break; case lir_unwind: s = "unwind"; break; case lir_convert: s = "convert"; break; case lir_alloc_object: s = "alloc_obj"; break; case lir_monaddr: s = "mon_addr"; break; // LIR_Op2 case lir_cmp: s = "cmp"; break; case lir_cmp_l2i: s = "cmp_l2i"; break; case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; case lir_cmp_fd2i: s = "comp_fd2i"; break; case lir_add: s = "add"; break; case lir_sub: s = "sub"; break; case lir_mul: s = "mul"; break; case lir_div: s = "div"; break; case lir_rem: s = "rem"; break; case lir_abs: s = "abs"; break; case lir_neg: s = "neg"; break; case lir_sqrt: s = "sqrt"; break; case lir_logic_and: s = "logic_and"; break; case lir_logic_or: s = "logic_or"; break; case lir_logic_xor: s = "logic_xor"; break; case lir_shl: s = "shift_left"; break; case lir_shr: s = "shift_right"; break; case lir_ushr: s = "ushift_right"; break; case lir_alloc_array: s = "alloc_array"; break; case lir_xadd: s = "xadd"; break; case lir_xchg: s = "xchg"; break; // LIR_Op3 case lir_idiv: s = "idiv"; break; case lir_irem: s = "irem"; break; case lir_fmad: s = "fmad"; break; case lir_fmaf: s = "fmaf"; break; // LIR_Op4 case lir_cmove: s = "cmove"; break; // LIR_OpJavaCall case lir_static_call: s = "static"; break; case lir_optvirtual_call: s = "optvirtual"; break; case lir_icvirtual_call: s = "icvirtual"; break; case lir_dynamic_call: s = "dynamic"; break; // LIR_OpArrayCopy case lir_arraycopy: s = "arraycopy"; break; // LIR_OpUpdateCRC32 case lir_updatecrc32: s = "updatecrc32"; break; // LIR_OpLock case lir_lock: s = "lock"; break; case lir_unlock: s = "unlock"; break; // LIR_OpDelay case lir_delay_slot: s = "delay"; break; // LIR_OpTypeCheck case lir_instanceof: s = "instanceof"; break; case lir_checkcast: s = "checkcast"; break; case lir_store_check: s = "store_check"; break; // LIR_OpCompareAndSwap case lir_cas_long: s = "cas_long"; break; case lir_cas_obj: s = "cas_obj"; break; case lir_cas_int: s = "cas_int"; break; // LIR_OpProfileCall case lir_profile_call: s = "profile_call"; break; // LIR_OpProfileType case lir_profile_type: s = "profile_type"; break; // LIR_OpAssert #ifdef ASSERT case lir_assert: s = "assert"; break; #endif case lir_none: ShouldNotReachHere();break; default: s = "illegal_op"; break;
} return s;
}
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